Results 31 to 40 of about 45,362 (262)
CAAI Transactions on Intelligence Technology, EarlyView., 2023 Abstract This research focuses on addressing the privacy issues in healthcare advancement monitoring with the rapid establishment of the decentralised communication system in the Internet of Medical Things (IoMT). An integrated blockchain homomorphic encryption standard with an in‐build supervised learning‐based smart contract is designed to improvise ...
Chandramohan Dhasarathan +7 more
wiley +1 more source
International Journal of Reconfigurable Computing, 2011 Limits of instruction-level parallelism and higher transistor density sustain the increasing need for multiprocessor systems: they are rapidly taking over both general-purpose and embedded processor domains.
Mateus B. Rutzig +7 more
doaj +1 more source
Late-Stage Optimization of Modern ILP Processor Cores via FPGA Simulation
Applied Sciences, 2022 Late-stage (post-RTL implementation) optimization is important in achieving target performance for realistic processor design. However, several challenges remain for modern out-of-order ILP (instruction-level-parallelism) processors, such as simulation ...
Mengqiao Lan +6 more
doaj +1 more source
IET Communications, EarlyView., 2022 Abstract The goal of this work is to investigate how the self‐awareness characteristic of autonomic computing, paired with existing performance optimization rules, may be used in applications to minimise multi‐core processor performance concerns. The suggested self‐awareness technique can assist applications in self‐execution while also assisting other
Surendra Kumar Shukla +8 more
wiley +1 more source
A case for merging the ILP and DLP paradigms [PDF]
, 1998 The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved using either paradigm on its ...
Espasa Sans, Roger +2 more
core +1 more source
IEEE Access, 2013 The adaptive Runge-Kutta (ARK) method on multi-general-purpose graphical processing units (GPUs) is used for solving large nonlinear systems of first-order ordinary differential equations (ODEs) with over ~ 10 000 variables describing a large genetic ...
Ahmad Al-Omari +3 more
doaj +1 more source
Hardware schemes for early register release [PDF]
, 2002 Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the size and number of ports of the ...
González Colás, Antonio María +3 more
core +1 more source
Register Saturation in Instruction Level Parallelism [PDF]
International Journal of Parallel Programming, 2005 The registers constraints are usually taken into account during the scheduling pass of an acyclic data dependence graph (DAG): any schedule of the instructions inside a basic block must bound the register requirement under a certain limit. In this work, we show how to handle the register pressure before the instruction scheduling of a DAG.
openaire +3 more sources
POWER: Parallel Optimizations With Executable Rewriting [PDF]
, 2011 The hardware industry's rapid development of multicore and many core hardware has outpaced the software industry's transition from sequential to parallel programs. Most applications are still sequential, and many cores on parallel machines remain unused.
Arora, Nipun +4 more
core +2 more sources
Accelerating Nested Conditionals on CGRA With Tag-Based Full Predication Method
IEEE Access, 2020 CGRA (Coarse-grained Reconfigurable Architecture) has been widely considered as one of the most promising computing architectures to exploit spatial parallelism.
Jiang Sha +3 more
doaj +1 more source