Results 41 to 50 of about 45,362 (262)
Late allocation and early release of physical registers [PDF]
, 2004 The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the ...
González Colás, Antonio María +4 more
core +2 more sources
Sensors, 2017 This paper aims to develop a low-cost, high-performance and high-reliability computing system to process large-scale data using common data mining algorithms in the Internet of Things (IoT) computing environment.
Yuling Fang +4 more
doaj +1 more source
Strategy of microscopic parallelism for Bitplane Image Coding [PDF]
, 2015 Recent years have seen the upraising of a new type of processors strongly relying on the Single Instruction, Multiple Data (SIMD) architectural principle.
Aulí-Llinàs, Francesc +4 more
core +1 more source
Vectorization of Program Code Containing Low Probability Regions in Computational Geometry Problems
Современные информационные технологии и IT-образование, 2022 Improving application performance is an important practical task for supercomputer calculations. Along with parallelization of calculations between cluster nodes (for example, using MPI tools), as well as multithreaded programming (for example, using ...
Alexey Rybakov
doaj +1 more source
From Physics Model to Results: An Optimizing Framework for Cross-Architecture Code Generation [PDF]
, 2013 Starting from a high-level problem description in terms of partial differential equations using abstract tensor notation, the Chemora framework discretizes, optimizes, and generates complete high performance codes for a wide range of compute ...
Blazewicz, Marek +8 more
core +4 more sources
Microarchitectural Characterization on a Mobile Workload
Applied Sciences, 2021 Geekbench is one of the most referenced cross-platform benchmarks in the mobile world. Most of its workloads are synthetic but some of them aim to simulate real-world behavior. In the mobile world, its microarchitectural behavior has been reported rarely
Woohyong Lee +3 more
doaj +1 more source
Understanding the thermal implications of multicore architectures [PDF]
, 2007 Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations by exploiting thread-level ...
Cai, Qiong +4 more
core +2 more sources
A Pipeline-Based ODE Solving Framework
IEEE AccessThe traditional parallel solving methods of ordinary differential equations (ODE) are mainly classified into task-parallelism, data-parallelism, and instruction-level parallelism.
Ruixia Cao, Shangjun Hou, Lin Ma
doaj +1 more source
IEEE Open Journal of Power Electronics, 2020 System-level electromagnetic transient (EMT) simulation of large-scale power converters with high-order nonlinear semiconductor switch models remains a challenge albeit it is essential for design preview. In this work, a multi-layer hierarchical modeling
Ning Lin, Ruimin Zhu, Venkata Dinavahi
doaj +1 more source
Thread partitioning and value prediction for exploiting speculative thread-level parallelism [PDF]
, 2004 Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find.
González Colás, Antonio María +2 more
core +2 more sources