Results 51 to 60 of about 45,362 (262)
Scalable IC Platform for Smart Cameras
EURASIP Journal on Advances in Signal Processing, 2005 Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas, software and IC development. In order to reduce cost, it is worthwhile to invest in a single architecture that can be scaled for the ...
Harry Broers +3 more
doaj +1 more source
An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems
Sensors, 2012 The VLIW architecture can be exploited to greatly enhance instruction level parallelism, thus it can provide computation power and energy efficiency advantages, which satisfies the requirements of future sensor-based systems.
Hu He, Xu Yang
doaj +1 more source
IEEE Access, 2023 In this paper, an improved multiplier architecture, utilizing dual mode logic (DML) targeting single-instruction-multiple-data (SIMD)-like systems is proposed.
Netanel Shavit +4 more
doaj +1 more source
, 1993 Instruction-level parallelism (ILP) is a set of processor and compiler design techniques that speed up program execution via the parallel execution of individual RISC-style operations, such as memory loads and stores, integer additions, and floating-point multiplications.
Joseph A. Fisher, B. Ramakrishna Rau
openaire +2 more sources
goSLP: Globally Optimized Superword Level Parallelism Framework
, 2018 Modern microprocessors are equipped with single instruction multiple data (SIMD) or vector instruction sets which allow compilers to exploit superword level parallelism (SLP), a type of fine-grained parallelism.
Amarasinghe, Saman, Mendis, Charith
core +1 more source
Quantifying the benefits of SPECint distant parallelism in simultaneous multithreading architectures [PDF]
, 1999 We exploit the existence of distant parallelism that future compilers could detect and characterise its performance under simultaneous multithreading architectures.
Ayguadé Parra, Eduard +4 more
core +1 more source
A Method to Detect Hazards in Pipeline Processor
MATEC Web of Conferences, 2017 In order to improve the throughput of the processors, pipeline technique is widely used to implement the instruction-level parallelism. However, this technique also leads to data hazards which has a great influence on the performance. This paper proposed
He Yihui +3 more
doaj +1 more source
Design Principles for Sparse Matrix Multiplication on the GPU
, 2018 We implement two novel algorithms for sparse-matrix dense-matrix multiplication (SpMM) on the GPU. Our algorithms expect the sparse input in the popular compressed-sparse-row (CSR) format and thus do not require expensive format conversion.
A Tiskin +11 more
core +1 more source
Advanced Materials Technologies, EarlyView.Recent efforts of memristor array‐based hardware neuromorphic computing are discussed for efficient application of VMM on‐chip level in terms of circuit integration and actual application of AI algorithms. The parallel data processing principle of VMM operation is briefly reviewed, and hardware VMM is presented including convolutional transformation ...
Jingon Jang, Sang‐gyun Gi
wiley +1 more source
TVB C++: A Fast and Flexible Back‐End for The Virtual Brain
Advanced Science, EarlyView.TVB C++ is a streamlined and fast C++ Back‐End for The Virtual Brain (TVB), designed to make it as flexible as TVB, and FAST. Another pillar is to be fully compatible with TVB so easy bindings can be created from Python. Users can easily configure TVB C++ to execute the same code but with enhanced performance and parallelism.
Ignacio Martín +7 more
wiley +1 more source