Results 61 to 70 of about 45,362 (262)
Thread level parallelism (TLP) is a common approach to achieve parallelism where Instruction level parallelism (ILP) is insufficient. Hardware multithreading is a prevalent approach in the micro-architecture layer for tolerating long events such as ...
Hananya Ribo, Shlomo Greenberg
doaj +1 more source
Container-based High-Performance Computing (HPC) is changing the way computation is performed and reproduced without sacrificing the raw performance compared to hypervisor-assisted virtualization technologies.
Animesh Kuity, Sateesh K. Peddoju
doaj +1 more source
A kinematically Bifurcated Metamaterial for Integrated Logic Operation and Computing
A family of 2n‐side kinematic polygonal modules with n decoupled inputs and 2n extreme configurations via kinematic bifurcation is proposed. It allows integrating seven basic logic gates on a quadrilateral module. Moreover, a minimized Parallel Computing Sum of Products function is developed, enabling all 2‐bit arithmetic (including division ...
Kaili Xi +6 more
wiley +1 more source
Empowering parallel computing with field programmable gate arrays [PDF]
After more than 30 years, reconfigurable computing has grown from a concept to a mature field of science and technology. The cornerstone of this evolution is the field programmable gate array, a building block enabling the configuration of a custom hardware ...
D'Hollander, Erik
core +2 more sources
This article presents the artificial synapse based on strontium titanate thin films via spin‐coating followed by forming gas annealing to introduce oxygen vacancies. Characterizations (X‐ray photoelectron spectroscopy, electron paramagnetic resonance, Ultraviolet photoelectron spectroscopy (UPS)) confirm increased oxygen vacancies and downward energy ...
Fandi Chen +16 more
wiley +1 more source
The Potential for a GPU-Like Overlay Architecture for FPGAs
We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation.
Jeffrey Kingyens, J. Gregory Steffan
doaj +1 more source
Accelerating SAR Image Registration Using Swarm-Intelligent GPU Parallelization
Image registration is an important processing step in synthetic aperture radar (SAR) image applications, such as change detection, and elevation extraction.
Yingbing Liu +5 more
doaj +1 more source
Object oriented execution model (OOM) [PDF]
This paper considers implementing the Object Oriented Programming Model directly in the hardware to serve as a base to exploit object-level parallelism, speculation and heterogeneous computing.
Cristal Kestelman, Adrián +5 more
core
This study introduces a real‐time light detection and ranging‐camera fusion framework for vehicle detection and tracking. Using a Gaussian mixture model‐based association and improved affinity metrics, the method enhances tracking reliability in dynamic conditions.
Muhammad Adeel Altaf, Min Young Kim
wiley +1 more source
PerPI: A Tool to Measure Instruction Level Parallelism [PDF]
We introduce and describe PerPI, a software tool analyzing the instruction level parallelism (ILP) of a program. ILP measures the best potential of a program to run in parallel on an ideal machine – a machine with infinite resources. PerPI is a programmer-oriented tool the function of which is to improve the understanding of how the algorithm and the ...
Goossens, Bernard +3 more
openaire +2 more sources

