Results 71 to 80 of about 45,362 (262)

RPPM : Rapid Performance Prediction of Multithreaded workloads on multicore processors [PDF]

, 2019
Analytical performance modeling is a useful complement to detailed cycle-level simulation to quickly explore the design space in an early design stage. Mechanistic analytical modeling is particularly interesting as it provides deep insight and does not ...
Akram, Shoaib, De Pestel, Sander, Eeckhout, Lieven, Van den Steen, Sam   +3 more
core   +2 more sources

Symbolic Reservoir Computing within Memristive Crossbar Arrays as a Cellular Automata

Advanced Intelligent Systems, EarlyView.
In quest of a neuro‐symbolic system with both strong intelligent computing capability and better explainability, a memristor crossbar array‐based cellular automata (symbolic model) for reservoir computing (neural network) is proposed and experimentally demonstrated using an algorithm–hardware codesign approach.
Yunpeng Guo, Chenfei Miao, Xinxin Wang, Xue Liu, Cheng Ma, Lidan Wang, Shukai Duan, Wenrui Duan, Huanglong Li   +8 more
wiley   +1 more source

Chip Design of Multithreaded and Pipelined RISC-V Microcontroller Unit

Engineering Proceedings
Multithreading is widely used in microcontroller unit (MCU) chips. Multithreaded hardware is composed of multiple identical single threads and provides instructions to different threads.
Mao-Hsu Yen, Yih-Hsia Lin, Tzu-Feng Lin, Yu-Hui Chen, Yuan-Fu Ku, Chien-Ting Kao   +5 more
doaj   +1 more source

A framework for FPGA functional units in high performance computing [PDF]

, 2010
FPGAs make it practical to speed up a program by defining hardware functional units that perform calculations faster than can be achieved in software. Specialised digital circuits avoid the overhead of executing sequences of instructions, and they make
Koltes, A., O'Donnell, J.T.
core   +1 more source

Securing Generative Artificial Intelligence with Parallel Magnetic Tunnel Junction True Randomness

Advanced Intelligent Systems, EarlyView.
True random numbers can protect generative artificial intelligence (GAI) models from attacks. A highly parallel, spin‐transfer torque magnetic tunnel junction‐based system is demonstrated that generates high‐quality, energy‐efficient random numbers.
Youwei Bao, Shuhan Yang, Hyunsoo Yang
wiley   +1 more source

Step‐Efficient Parallel Implementation of n‐bit Full Adders Using Stateful Logic in Memristor Crossbar Arrays

Advanced Intelligent Systems, EarlyView.
A step‐efficient stateful logic architecture is demonstrated using a fabricated 32 × 32 memristor crossbar array, enabling parallel n‐bit full adder operations directly in memory. By optimizing load resistance and voltage configurations, the circuit achieves reliable NIMP, AND, and OR logic operations with minimized computational steps, enhanced ...
Jinwoo Park, Jungjin Lee, Sangwook Youn, Hyungjin Kim   +3 more
wiley   +1 more source

The Future of Instruction-Level Parallelism (ILP)

2025 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
High-performance processors have long used instruction-level parallelism (ILP) to achieve performance, but in the past decade processor vendors have dramatically increased their reliance upon this technique. We therefore take another look at the theoretical limits of ILP, in order to evaluate challenges and opportunities for processor architectures ...
Chadwick, Alexandra W, Erdős, Márton, Bora, Utpal, Bhosale, Akshay, Lytton, Bob, Guo, Yuxin, Cooper, Richard, Gabrielli, Giacomo, Jones, Timothy M   +8 more
openaire   +1 more source

Ecolabels as Heuristic Cues: Exploring the Role of Ecolabels in Food Attribute Inferences

Business Strategy and the Environment, EarlyView.
ABSTRACT This study presents a novel approach by examining the role of environmental labels (e.g., ecolabels) as heuristic cues in consumer inferences, beyond their traditional informational function. The research evaluated the influence of the presence, number, and type (real or fake) of ecolabels on consumer inferences of an extra virgin olive oil ...
Francisco José Torres‐Peña, Manuel Parras‐Rosa, Carla Marano‐Marcolini, Francisco José Torres‐Ruiz   +3 more
wiley   +1 more source

Implementing OpenMP 4.0 for the NVIDIA PTX architecture in GCC compiler

Труды Института системного программирования РАН, 2018
The paper describes the approach used in implementing OpenMP offloading to NVIDIA accelerators in GCC. Offloading refers to a new capability in OpenMP 4.0 specification update that allows the programmer to specify regions of code that should be executed ...
A. V. Monakov, V. A. Ivanishin
doaj   +1 more source

Array languages and the N-body problem [PDF]

, 2013
This paper is a description of the contributions to the SICSA multicore challenge on many body planetary simulation made by a compiler group at the University of Glasgow.
Cockshott, P., Gdura, Y., Keir, P.
core   +1 more source