Results 1 to 10 of about 298,312 (311)
RISC-V Instruction Set Architecture Extensions: A Survey [PDF]
IEEE Access, 2023 RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions.
Enfang Cui, Tianzheng Li, Qian Wei
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Understanding evolutionary potential in virtual CPU instruction set architectures. [PDF]
PLoS ONE, 2013 We investigate fundamental decisions in the design of instruction set architectures for linear genetic programs that are used as both model systems in evolutionary biology and underlying solution representations in evolutionary computation.
David M Bryson, Charles Ofria
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Phantom-GRAPE: numerical software library to accelerate collisionless $N$-body simulation with SIMD instruction set on x86 architecture [PDF]
, 2012 (Abridged) We have developed a numerical software library for collisionless N-body simulations named "Phantom-GRAPE" which highly accelerates force calculations among particles by use of a new SIMD instruction set extension to the x86 architecture, AVX ...
Nitadori, Keigo +3 more
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Improving Instruction Set Architecture learning results [PDF]
Proceedings of the 2004 workshop on Computer architecture education held in conjunction with the 31st International Symposium on Computer Architecture - WCAE '04, 2004 In this article, we put forward a new methodology and strategy for teaching the Instruction Set Architecture in a "Computer Organization" unit. This unit belongs to the second year of the undergraduate program in Computer Science at our University.
José M. Claver +2 more
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IET Information Security, 2022 A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still be ...
Yuze Wang, Peng Liu, Yingtao Jiang
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Engineering an Optimized Instruction Set Architecture for AMIDAR Processors [PDF]
Architecture of Computing Systems – ARCS 202033rd International Conference, 2020 Schwarz A, Hochberger C.
europepmc +3 more sources
Block-aware instruction set architecture [PDF]
ACM Transactions on Architecture and Code Optimization, 2006 Instruction delivery is a critical component for wide-issue, high-frequency processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and bandwidth are limited by instruction-cache misses, multicycle instruction-cache accesses, and target or direction mispredictions for control-flow operations ...
Ahmad Zmily, Christos Kozyrakis
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SeaBird Instruction Set Architecture Documentation
Technical documentation for the SeaBird ISA.
Rodriguez, Ulises
+4 more sources
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture
, 2014 This document describes the rapidly maturing design for the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA), which is being developed by SRI International and the University of Cambridge. The document is intended to capture our evolving architecture, as it is being refined, tested, and formally analyzed.
Robert N. M. Watson +9 more
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On Internally Tagged Instruction Set Architectures [PDF]
IEEE Computer Architecture LettersEmad Jacob Maroun
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