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ARMISS: An Instruction Set Simulator for the ARM Architecture
2008 International Conference on Embedded Software and Systems, 2008The development efficiency of embedded systems is highly pressured due to the pursuit of short time-to-market of embedded products. In traditional design flow, although software can be developed in parallel with the hardware platform, it can only be tested and verified after the platform is fabricated.
Ge Yu +4 more
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IEEE 1149.4 Architecture and Instruction Set [PDF]
, 1999 Similar to the other chapters in this book, this chapter is written with readers in mind who may not be familiar with the 1149.1 digital test standard because they are more familiar with analog and mixed-signal ICs, which typically do not use boundary-scan.
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A functional specification language for instruction set architectures
Proceedings of 1994 IEEE International Conference on Computer Languages (ICCL'94), 2002Application-specific programmable processing systems consist of not only a processor, but also the software that runs on it. In order to support development of such systems, a design environment must support both hardware and software development. Unfortunately, there are no specification languages for processors that are suitable for such dual use ...
Todd A. Cook, Ed Harcourt
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Design of Architecture and Instruction-set of RASIP for SDR
2006 International Conference on Advanced Computing and Communications, 2006In this paper, a novel methodology has been presented for designing the architecture and its instruction-set for Reconfigurable Application Specific Instruction-set Processor (RASIP) for Software Defined Radio (SDR). We have described the architectural aspects by giving complete functionality of different modules present in the architecture ...
R. C. Joshi +3 more
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CReconfigurable finite field instruction set architecture
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, 2007Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be ...
Fernando Martinez-Vallin +2 more
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Implementation-independent model of an instruction set architecture using VHDL
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1993A novel methodology is presented which allows the creation of implementation-independent functional models of systems. The methodology uses the VHSIC (very high speed integrated circuit) hardware description language (VHDL) which leads to the possibility of creating a unified design environment supporting system modeling at various stages of the design
M.H. Salinas +2 more
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2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)., 2005
An instruction set architecture scheme (ISA scheme) is proposed for multiple fixed-width instruction sets in embedded RISC processor. The ISA scheme can achieve efficient ISA change in instruction level. Besides, compared to current conditional execution methods, the parallel conditional execution (PCE) supported by ISA scheme has smaller code size and
Ming-Chuan Huang +8 more
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An instruction set architecture scheme (ISA scheme) is proposed for multiple fixed-width instruction sets in embedded RISC processor. The ISA scheme can achieve efficient ISA change in instruction level. Besides, compared to current conditional execution methods, the parallel conditional execution (PCE) supported by ISA scheme has smaller code size and
Ming-Chuan Huang +8 more
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An Isabelle/HOL Formalisation of the SPARC Instruction Set Architecture and the TSO Memory Model
Journal of automated reasoning, 2020Zhé Hóu +5 more
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An instruction set architecture for the 1990s: parallel and retargetable
Digest of Papers. COMPCON Spring 89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, 2003The G ISA has proved its retargetability by being implemented on three disparate hardware platforms. The first implementation was on a platform with software address translation and floating point; later versions incorporated these features in hardware. The SPS-1 and SPS-2 have distributed memory and use message passing.
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Nebula Instruction Set Architecture (ISA) Evaluation.
1984Abstract : This effort conducted a review of MIL-STD-1862A (Nebula) Instruction Set Architecture (ISA). Nebula is proposed as a major ISA for embedded computer systems in the late 1980's and the 1990's. Nebula was reviewed from a number of viewpoints by independent reviewers.
D. J. DeWitt +4 more
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