Results 11 to 20 of about 539,422 (337)
RISC-V Instruction Set Architecture Extensions: A Survey [PDF]
IEEE Access, 2023 RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions.
Enfang Cui, Tianzheng Li, Qian Wei
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An Instruction Set Architecture for Machine Learning [PDF]
ACM Transactions on Computer Systems, 2018 Machine Learning (ML) are a family of models for learning from the data to improve performance on a certain task. ML techniques, especially recent renewed neural networks (deep neural networks), have proven to be efficient for a broad range of applications. ML techniques are conventionally executed on general-purpose processors (such as CPU and GPGPU),
Yunji Chen +10 more
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eQASM: An Executable Quantum Instruction Set Architecture [PDF]
2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018 A widely-used quantum programming paradigm comprises of both the data flow and control flow. Existing quantum hardware cannot well support the control flow, significantly limiting the range of quantum software executable on the hardware. By analyzing the constraints in the control microarchitecture, we found that existing quantum assembly languages are
Xiang Fu +15 more
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PISA-DMA: Processing-in-Memory Instruction Set Architecture Using DMA [PDF]
IEEE Access, 2023 Processing-in-memory (PIM) has attracted attention to overcome the memory bandwidth limitation, especially for computing memory-intensive DNN applications.
Won Jun Lee +3 more
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SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems [PDF]
Micro, 2021 Simple graph algorithms such as PageRank have been the target of numerous hardware accelerators. Yet, there also exist much more complex graph mining algorithms for problems such as clustering or maximal clique listing.
Maciej Besta +17 more
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Phantom-GRAPE: Numerical software library to accelerate collisionless N-body simulation with SIMD instruction set on x86 architecture [PDF]
, 2012 (Abridged) We have developed a numerical software library for collisionless N-body simulations named "Phantom-GRAPE" which highly accelerates force calculations among particles by use of a new SIMD instruction set extension to the x86 architecture, AVX ...
Ataru Tanikawa +3 more
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Improving Instruction Set Architecture learning results [PDF]
Proceedings of the 2004 workshop on Computer architecture education held in conjunction with the 31st International Symposium on Computer Architecture - WCAE '04, 2004 In this article, we put forward a new methodology and strategy for teaching the Instruction Set Architecture in a "Computer Organization" unit. This unit belongs to the second year of the undergraduate program in Computer Science at our University.
José M. Claver +2 more
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Formalizing SPARCv8 instruction set architecture in Coq [PDF]
Science of Computer Programming, 2017 The SPARCv8 instruction set architecture (ISA) has been widely used in various processors for workstations, embedded systems, and space missions. In order to formally verify the correctness of embedded operating systems running on SPARCv8 processors, one has to formalize the semantics of SPARCv8 ISA.
Xinyu Feng +3 more
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Transactions on Cryptographic Hardware and Embedded Systems, 2020 In this paper, we present an instruction set coprocessor architecture for lattice-based cryptography and implement the module lattice-based post-quantum key encapsulation mechanism (KEM) Saber as a case study.
Sujoy Sinha Roy, Andrea Basso
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Understanding evolutionary potential in virtual CPU instruction set architectures. [PDF]
PLoS ONE, 2013 We investigate fundamental decisions in the design of instruction set architectures for linear genetic programs that are used as both model systems in evolutionary biology and underlying solution representations in evolutionary computation.
David M Bryson, Charles Ofria
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