Results 11 to 20 of about 298,312 (311)

A Robust and Portable All-Digital TRNG Circuit for Extending the Instruction Set Architecture of RISC-V Processors

IEEE Access
All-digital True Random Number Generators (TRNGs) play a crucial role in enhancing hardware security by providing native entropy sources directly within the processor pipeline.
Luca Crocetti, Ettore Noccetti, Pietro Nannipieri, Stefano Di Matteo, Ivan Sarno, Sergio Saponara   +5 more
doaj   +2 more sources

PISA-DMA: Processing-in-Memory Instruction Set Architecture Using DMA

IEEE Access, 2023
Processing-in-memory (PIM) has attracted attention to overcome the memory bandwidth limitation, especially for computing memory-intensive DNN applications.
Won Jun Lee, Chang Hyun Kim, Yoonah Paik, Seon Wook Kim   +3 more
doaj   +1 more source

A Multi-One Instruction Set Computer for Microcontroller Applications

IEEE Access, 2021
This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to ...
Marco Crepaldi, Andrea Merello, Mirco Di Salvo   +2 more
doaj   +1 more source

Back-end porting of FT_MX based on LLVM compilation architecture [PDF]

MATEC Web of Conferences, 2021
The processor FT_MX is a high-performance chip independently developed by the National University of Defense Technology, with an innovative architecture and instruction set.
Deng Ping, Zhu Xiaolong, Sun Haiyan, Ren Yi   +3 more
doaj   +1 more source

Tensor Instruction Generation Optimization Fusing with Loop Partitioning [PDF]

Jisuanji kexue, 2023
The tensor compiler compiles the tensor algorithm and schedule of the operator into the code of the target hardware.In order to accelerate tensor operation,the special processor in the field of deep learning is designed as a special architecture with ...
LIANG Jiali, HUA Baojian, SU Shaobo
doaj   +1 more source

The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension

IEEE Access, 2023
Edge computing is becoming increasingly popular in artificial intelligence (AI) application development due to the benefits of local execution. One widely used approach to overcome hardware limitations in edge computing is heterogeneous computing, which ...
Hyun Woo Oh, Seung Eun Lee
doaj   +1 more source

Compiling Optimization Method of Address Immediate Value Based on C-SKY CPU [PDF]

Jisuanji gongcheng, 2016
As Reduced Instruction Set Computer(RISC) architecture processors generally use fixed-length instructions,they have to perform the function of long jump instruction in Complex Instruction Set Computer(CISC) architecture processors by a literal pool.This ...
LIAN Yulong,SHI Zheng,LI Chunqiang,WANG Huibin,SHANG Yunhai
doaj   +1 more source

Optimization of beam pointing algorithm based on PowerPC

Dianzi Jishu Yingyong, 2021
Based on PowerPC architecture, this paper proposes an optimization strategy of beam pointing algorithm, which is realized from the trigonometric function calculation optimization, floating point arithmetic optimization, loop nesting optimization, and ...
Lei Shulan, Wu Huixiang, Li Wenxue
doaj   +1 more source

Special Instruction Set Processor for Convolutional Neural Network Based on RISC-V [PDF]

Jisuanji gongcheng, 2021
The x86-based and ARM-based CPU are limited by the patent authorization,which increases their customization cost and reduces the flexibility.To address the problem,this paper chooses the open-source instruction set architecture,RISC-V,to build an special
LIAO Hansong, WU Zhaohui, LI Bin
doaj   +1 more source

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

IEEE Access, 2020
This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA).
Nguyen My Qui, Chang Hong Lin, Poki Chen
doaj   +1 more source