Results 281 to 290 of about 298,312 (311)

Reduced instruction set computer architecture

Proceedings of the IEEE, 1988
A tutorial on the reduced instruction set computer (RISC) approach is presented and the key design issues involved in RISC architecture are highlighted. The results of a number of studies on the instruction execution characteristics of compiled high-level-language programs are examined first.
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CReconfigurable finite field instruction set architecture

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, 2007
Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be ...
Nathan Jachimie, Fernando Martinez-Vallin, Jafar Saniie   +2 more
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EMULATION FOR MULTIPLE INSTRUCTION SET ARCHITECTURES

2021
System emulation and firmware re-hosting are popular techniques to answer various security and performance related questions, such as, does a firmware contain security vulnerabilities or meet timing requirements when run on a specific hardware platform.
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Architecture and Instruction Sets

1985
The usual meaning of architecture stems from the design of buildings and is concerned with such things as the way that the purpose of the building is related to the use of space, the size and shape of the structure, the materials used, the aesthetic qualities of the building (does it look good?) and so on. An architect, or team of architects, will have
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Instruction set extension exploration in multiple-issue architecture

Proceedings of the conference on Design, automation and test in Europe, 2008
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized instruction set extension (ISE) or to increase instruction issue width. Previous studies have shown that deploying ISE in multiple-issue architecture can significantly improve ...
I-Wei Wu, Zhi-Yuan Chen, Jyh-Jiun Shann, Chung-Ping Chung   +3 more
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Instruction set architecture of an efficient pipelined dataflow architecture

[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track, 2003
A highly pipelined static dataflow architecture based on an argument-fetching data-driven principle has recently been proposed. It separates the data-driven instruction scheduling mechanism from the actual instruction execution unit, avoiding the unnecessary overhead of data token movement that exists in other proposals of dataflow architectures.
G.R. Gao, R. Tio
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An architectural framework for supporting heterogeneous instruction-set architectures

Computer, 1993
An architectural framework that allows software applications and operating system code written for a given instruction set to migrate to different, higher performance architectures is described. The framework provides a hardware mechanism that enhances application performance while keeping the same program behavior from a user perspective.
G.M. Silberman, K. Ebcioglu
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Instruction set architecture scheme for multiple fixed-width instruction sets and conditional execution

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)., 2005
An instruction set architecture scheme (ISA scheme) is proposed for multiple fixed-width instruction sets in embedded RISC processor. The ISA scheme can achieve efficient ISA change in instruction level. Besides, compared to current conditional execution methods, the parallel conditional execution (PCE) supported by ISA scheme has smaller code size and
null Bor-Sung Liang, null June-Yuh Wu, null Jih-Yiing Lin, null Ming-Chuan Huang, null Chi-Shaw Lai, null Yun-Yin Lien, null Ching-Hua Chang, null Pei-Lin Tsai, null Ching-Peng Lin   +8 more
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Nebula Instruction Set Architecture (ISA) Evaluation.

1984
Abstract : This effort conducted a review of MIL-STD-1862A (Nebula) Instruction Set Architecture (ISA). Nebula is proposed as a major ISA for embedded computer systems in the late 1980's and the 1990's. Nebula was reviewed from a number of viewpoints by independent reviewers.
D. J. DeWitt, A. Demers, R. D. Cowles, H. Boral, R. D. Arnold   +4 more
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Instruction set architecture to control instruction fetch on pipelined processors

1997 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM. 10 Years Networking the Pacific Rim, 1987-1997, 2002
Instruction fetching is usually the default action related to the program counter, and it is affected by the execution of a branch instruction. However, the processor does not know about the timing of a branch until it fetches a branch instruction, and it must start processing the branch just after fetching a branch instruction.
S. Okamoto, M. Sowa
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