Results 291 to 300 of about 539,422 (337)
Some of the next articles are maybe not open access.
Cambricon: An Instruction Set Architecture for Neural Networks
2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), 2016Neural Networks (NN) are a family of models for a broad range of emerging machine learning and pattern recondition applications. NN techniques are conventionally executed on general-purpose processors (such as CPU and GPGPU), which are usually not energy-efficient since they invest excessive hardware resources to flexibly support various workloads ...
Yunji Chen +7 more
openaire +3 more sources
Parallelism and the ARM instruction set architecture
Computer, 2005Over the past few years, the ARM reduced-instruction-set computing (RISC) processor has evolved to offer a family of chips that range up to a full-blown multiprocessor. Embedded applications' demand for increasing levels of performance and the added efficiency of key new technologies has driven the ARM architecture's evolution.
Goodacre, J, Sloss, AN
openaire +3 more sources
A Quantum Pipeline for an Executable Quantum Instruction Set Architecture
IEEE Computer Society Annual Symposium on VLSI, 2020The existence of algorithm to machine gap has been accepted by the quantum computing domain experts, as the research community is struggling to realize the real power of quantum computing.
Suvadip Batabyal, Lovekush Sharma
semanticscholar +1 more source
Security Analysis of Processor Instruction Set Architecture for Enforcing Control-Flow Integrity
HASP@ISCA, 2019Intel has developed Control-flow Enforcement Technology (CET) [27] that provides CPU instruction set architecture (ISA) capabilities to defend against Return-oriented Programming (ROP) and call/jmp-oriented programming (COP/JOP) style control-flow ...
Vedvyas Shanbhogue, D. Gupta, R. Sahita
semanticscholar +1 more source
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security - CCS '13, 2013 Code injection attacks continue to pose a threat to today's computing systems, as they exploit software vulnerabilities to inject and execute arbitrary, malicious code. Instruction Set Randomization (ISR) is able to protect a system against remote machine code injection attacks by randomizing the instruction set of each process.
Papadogiannakis A. +3 more
openaire +1 more source
Computer architecture and instruction set design
Proceedings of the June 4-8, 1973, national computer conference and exposition on - AFIPS '73, 1973A group of computer scientists and mathematicians at Brown University has been engaged in the study of computer graphics for the past eight years. During the course of these studies a variety of topics has been investigated, in particular, during the last few years, the use of microprogramming for implementing graphics systems. In early 1971, Professor
M. J. Michel +4 more
openaire +2 more sources
Multiple instruction sets architecture (MISA)
2011 International Conference on Energy Aware Computing, 2011In the computer hardware industry, there are currently two highly successful instruction set architectures (ISAs): the CISC X86 ISA which is an established standard architecture in the personal computer and server markets, and the RISC ARM ISA which is currently used in many ultra-mobile computing devices, such as smart-phones and tablets.
Hussein Karaki, Haitham Akkary
openaire +2 more sources