Results 301 to 310 of about 539,422 (337)

Distributed instruction set computer architecture

IEEE Transactions on Computers, 1991
The Distributed Instruction Set Computer Architecture (DISC) is proposed as a fine-grained multiprocessing computer architecture. DISC uses a parallel instruction set and a distributed control mechanism to explore fine-grained, parallel processing in a multiple-functional-unit system.
L. Wang, C.-L. Wu
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Mk14 Architecture and Instruction Set

1980
To program the Mk14 effectively you must become familiar with the whole range of SC/MP instructions. There are 46 instructions in the SC/MP instruction set — 24 single-byte instructions and 22 double-byte instructions. Single-byte instructions produce actions entirely within the SC/MP microprocessor, whereas double-byte instructions mainly relate to ...
Rodney Dale, Ian Williamson
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Defining the instruction set architecture

2004
It's like building a bridge. Once the main lines of the structure are right, then the details miraculously fit. The problem is the overall design. Freeman Dyson in Freeman Dyson: Mathematician, Physicist, and Writer, Interview with Donald J. Albers, The College Mathematics Journal, 25, No. 1, January 1994 .
David J. Lilja, Sachin S. Sapatnekar
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EMULATION FOR MULTIPLE INSTRUCTION SET ARCHITECTURES

2021
System emulation and firmware re-hosting are popular techniques to answer various security and performance related questions, such as, does a firmware contain security vulnerabilities or meet timing requirements when run on a specific hardware platform.
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An architectural framework for supporting heterogeneous instruction-set architectures

Computer, 1993
An architectural framework that allows software applications and operating system code written for a given instruction set to migrate to different, higher performance architectures is described. The framework provides a hardware mechanism that enhances application performance while keeping the same program behavior from a user perspective.
Gabriel Mauricio Silberman, Kemal Ebcioglu   +1 more
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Instruction set architecture of an efficient pipelined dataflow architecture

[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track, 2003
A highly pipelined static dataflow architecture based on an argument-fetching data-driven principle has recently been proposed. It separates the data-driven instruction scheduling mechanism from the actual instruction execution unit, avoiding the unnecessary overhead of data token movement that exists in other proposals of dataflow architectures.
R. Tio, Guang R. Gao
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Reduced instruction set computer architecture

Proceedings of the IEEE, 1988
A tutorial on the reduced instruction set computer (RISC) approach is presented and the key design issues involved in RISC architecture are highlighted. The results of a number of studies on the instruction execution characteristics of compiled high-level-language programs are examined first.
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Instruction set extension exploration in multiple-issue architecture

Proceedings of the conference on Design, automation and test in Europe, 2008
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized instruction set extension (ISE) or to increase instruction issue width. Previous studies have shown that deploying ISE in multiple-issue architecture can significantly improve ...
I-Wei Wu, Chung-Ping Chung, Jyh-Jiun Shann, Zhi-Yuan Chen   +3 more
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A reversible instruction set architecture and algorithms

Proceedings Workshop on Physics and Computation. PhysComp '94, 2002
We describe a reversible instruction set architecture using recently developed reversible logic design techniques. Such an architecture has the dual advantage of being able to run backwards and of being, in theory, implementable so as to dissipate less than log 2 kT joules per bit operation. We analyze several basic control structures and algorithms on
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Instruction set architecture to control instruction fetch on pipelined processors

1997 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM. 10 Years Networking the Pacific Rim, 1987-1997, 2002
Instruction fetching is usually the default action related to the program counter, and it is affected by the execution of a branch instruction. However, the processor does not know about the timing of a branch until it fetches a branch instruction, and it must start processing the branch just after fetching a branch instruction.
S. Okamoto, M. Sowa
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