Results 321 to 330 of about 539,422 (337)

A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture

IEEE computer architecture letters, 2017
Jorge A. Martínez, J. A. Maestro, P. Reviriego   +2 more
semanticscholar   +1 more source

50 Years of computer architecture: From the mainframe CPU to the domain-specific tpu and the open RISC-V instruction set

IEEE International Solid-State Circuits Conference, 2018
D. Patterson
semanticscholar   +1 more source

A RISC-V instruction set processor-micro-architecture design and analysis

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), 2016
Aneesh Raveendran, Vinayak Patil, David Selvakumar, Vivian Desalphine   +3 more
semanticscholar   +1 more source

Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm

Mediterranean Conference on Embedded Computing, 2014
Roel Jordans, L. Józwiak, H. Corporaal
semanticscholar   +1 more source

Towards a RISC instruction set architecture for the 32-bit VLIW DSP processor core

2014 IEEE REGION 10 SYMPOSIUM, 2014
Khoi-Nguyen Le-Huu, Diem N. Ho, Anh-Vu Dinh-Duc, T. Vu   +3 more
semanticscholar   +1 more source

Pydgin: generating fast instruction set simulators from simple architecture descriptions with meta-tracing JIT compilers

IEEE International Symposium on Performance Analysis of Systems and Software, 2015
Derek Lockhart, Berkin Ilbeyi, C. Batten
semanticscholar   +1 more source

Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs

Mediterranean Conference on Embedded Computing, 2013
Roel Jordans, R. Corvino, L. Józwiak, H. Corporaal   +3 more
semanticscholar   +1 more source

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

Design Automation Conference, 2013
Harry Wagstaff, Miles Gould, Björn Franke, N. Topham   +3 more
semanticscholar   +1 more source

Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit

IEEE Computer Society Annual Symposium on VLSI, 2012
Oliver Arnold, Benedikt Noethen, G. Fettweis   +2 more
semanticscholar   +1 more source

The DLX instruction set architecture handbook

Microelectronics Journal, 1997
openaire   +2 more sources