Results 31 to 40 of about 298,312 (311)
Automatic C Compiler Generation from Architecture Description Language ISAC [PDF]
, 2011 This paper deals with retargetable compiler generation. After an introduction to application-specific instruction set processor design and a review of code generation in compiler backends, ISAC architecture description language is introduced.
Hranac, Jan +4 more
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MOM: a matrix SIMD instruction set architecture for multimedia applications [PDF]
, 1999 MOM is a novel matrix-oriented ISA paradigm for multimedia applications, based on fusing conventional vector ISAs with SIMD ISAs such as MMX. This paper justifies why MOM is a suitable alternative for the multimedia domain due to its efficiency handling ...
Corbal San Adrián, Jesús +2 more
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Addressing Mode Extension to the ARM/Thumb Architecture
Advances in Electrical and Computer Engineering, 2014 In this paper, two new addressing modes are introduced to the 16-bit Thumb instruction set architecture to improve performance of the ARM/Thumb processors.
KIM, D.-H.
doaj +1 more source
eQASM: An Executable Quantum Instruction Set Architecture [PDF]
2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2019 A widely-used quantum programming paradigm comprises of both the data flow and control flow. Existing quantum hardware cannot well support the control flow, significantly limiting the range of quantum software executable on the hardware. By analyzing the constraints in the control microarchitecture, we found that existing quantum assembly languages are
X. Fu +15 more
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Comprehensive Review of Research on Dynamic Binary Translation Techniques [PDF]
Jisuanji kexue yu tansuoSolving compatibility issues in programs is crucial for building a domestic software ecosystem. With the diversification of computer architectures, ensuring software runs smoothly across different platforms and hardware environments has become an urgent ...
ZHANG Jin, SHAN Zehu, LIU Xiaodong, WANG Wenzhu, YU Jie, PENG Long, XIE Qiyou
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Analysis on the Possibility of RISC-V Adoption [PDF]
, 2020 As the interface between hardware and software, Instruction Set Architectures (ISAs) play a key role in the operation of computers. While both hardware and software have continued to evolve rapidly over time, ISAs have undergone minimal change. Since its
Scott, Ian
core
Research on LLM Vector Dot Product Acceleration Based on RISC-V Matrix Instruction Set Extension [PDF]
Jisuanji kexueConsidering the high-performance and low-power requirements of edge AI,this paper designs a specialized instruction set processor for edge AI based on the RISC-V instruction set architecture,addressing practical issues in digital signal processing for ...
CHEN Xuhao, HU Sipeng, LIU Hongchao, LIU Boran, TANG Dan, ZHAO Di
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Transactions on Cryptographic Hardware and Embedded Systems, 2020 In this paper, we present an instruction set coprocessor architecture for lattice-based cryptography and implement the module lattice-based post-quantum key encapsulation mechanism (KEM) Saber as a case study.
Sujoy Sinha Roy, Andrea Basso
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A Highly-Efficient and Tightly-Connected Many-Core Overlay Architecture
IEEE Access, 2021 The technology advances of CPU (Central Processing Unit) architecture alternate between generalization and specialization. In the past decade, the general performance has been enhanced while addressing the new brick walls that include power, memory, and ...
Riadh Ben Abdelhamid +2 more
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BPFabric: Data Plane Programmability for Software Defined Networks [PDF]
, 2017 In its current form, OpenFlow, the de facto implementation of SDN, separates the network’s control and data planes allowing a central controller to alter the matchaction pipeline using a limited set of fields and actions.
Jouet, Simon, Pezaros, Dimitrios P.
core +1 more source