An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures [PDF]
International Symposium on Computer Architecture, 2005 Steven Balensiefer +2 more
openalex +2 more sources
On Architectural Support for Instruction Set Randomization [PDF]
ACM Transactions on Architecture and Code Optimization, 2020 Instruction Set Randomization (ISR) is able to protect against remote code injection attacks by randomizing the instruction set of each process. Thereby, even if an attacker succeeds to inject code, it will fail to execute on the randomized processor.
Christou, George +4 more
openaire +2 more sources
Low Power Reduced Instruction Set Architecture Using Clock Gating Technique
Symposium on VLSI Circuits, 2013 M. Kamaraju, G. Chinavenkateswararao
openalex +2 more sources
A Multi-One Instruction Set Computer for Microcontroller Applications
IEEE Access, 2021 This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to ...
Marco Crepaldi +2 more
doaj +1 more source
Back-end porting of FT_MX based on LLVM compilation architecture [PDF]
MATEC Web of Conferences, 2021 The processor FT_MX is a high-performance chip independently developed by the National University of Defense Technology, with an innovative architecture and instruction set.
Deng Ping +3 more
doaj +1 more source
Tensor Instruction Generation Optimization Fusing with Loop Partitioning [PDF]
Jisuanji kexue, 2023 The tensor compiler compiles the tensor algorithm and schedule of the operator into the code of the target hardware.In order to accelerate tensor operation,the special processor in the field of deep learning is designed as a special architecture with ...
LIANG Jiali, HUA Baojian, SU Shaobo
doaj +1 more source
SIMD2: a generalized matrix instruction set for accelerating tensor computation beyond GEMM [PDF]
International Symposium on Computer Architecture, 2022 Matrix-multiplication units (MXUs) are now prevalent in every computing platform. The key attribute that makes MXUs so successful is the semiring structure, which allows tiling for both parallelism and data reuse.
Yunan Zhang, Po-An Tsai, Hung-Wei Tseng
semanticscholar +1 more source
N-body simulation for self-gravitating collisional systems with a new SIMD instruction set extension to the x86 architecture, Advanced Vector eXtensions [PDF]
, 2011 We present a high-performance N-body code for self-gravitating collisional systems accelerated with the aid of a new SIMD instruction set extension of the x86 architecture: Advanced Vector eXtensions (AVX), an enhanced version of the Streaming SIMD ...
Ataru Tanikawa +3 more
openalex +3 more sources
IEEE Access, 2023 Edge computing is becoming increasingly popular in artificial intelligence (AI) application development due to the benefits of local execution. One widely used approach to overcome hardware limitations in edge computing is heterogeneous computing, which ...
Hyun Woo Oh, Seung Eun Lee
doaj +1 more source
Similarity Metric Method for Binary Basic Blocks of Cross-Instruction Set Architecture
Proceedings 2020 Workshop on Binary Analysis Research, 2020 —Basic block similarity analysis is a fundamental technique in many machine learning-based binary program analysis methods. The key to basic block similarity analysis is mapping the semantic information of the basic block to a fixed-dimension vector ...
Xiaochuan Zhang +4 more
semanticscholar +1 more source