Results 41 to 50 of about 539,422 (337)
Optimization of beam pointing algorithm based on PowerPC
Dianzi Jishu Yingyong, 2021 Based on PowerPC architecture, this paper proposes an optimization strategy of beam pointing algorithm, which is realized from the trigonometric function calculation optimization, floating point arithmetic optimization, loop nesting optimization, and ...
Lei Shulan, Wu Huixiang, Li Wenxue
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Special Instruction Set Processor for Convolutional Neural Network Based on RISC-V [PDF]
Jisuanji gongcheng, 2021 The x86-based and ARM-based CPU are limited by the patent authorization,which increases their customization cost and reduces the flexibility.To address the problem,this paper chooses the open-source instruction set architecture,RISC-V,to build an special
LIAO Hansong, WU Zhaohui, LI Bin
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Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis [PDF]
IEEE Conference on High Performance Extreme Computing, 2022 Graphics Processing Units (GPUs) are now considered the leading hardware to accelerate general-purpose workloads such as AI, data analytics, and HPC.
H. Abdelkhalik +3 more
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IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2020 This article presents the design and implementation of an embedded programmable processor with a custom instruction set architecture for efficient realization of artificial neural networks (ANNs). The ANN processor architecture is scalable, supporting an
D. Valencia, S. F. Fard, A. Alimohammad
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IEEE Access, 2020 This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA).
Nguyen My Qui, Chang Hong Lin, Poki Chen
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Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms
Cryptography, 2022 The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms.
Görkem Nişancı +2 more
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RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems
IEEE Access, 2021 Redundant number systems (RNS) are a well-known technique to speed up arithmetic circuits. However, in a complete CPU, arithmetic circuits using RNS were only included on subcircuit level e.g. inside the Arithmetic Logic Unit (ALU) for realization of the
Marc Reichenbach +3 more
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Optimization Strategy of FFmpeg Multimedia Algorithm Library Based on RISC-V [PDF]
Jisuanji gongcheng, 2023 The widespread application of RISC-V processors has made the high-performance implementation of FFmpeg multimedia algorithm library on the RISC-V platform increasingly important.This study proposes a series of RISC-V architecture-based optimization ...
ZHANG Zhen, LIANG Jun, JIA Haipeng, ZHANG Yunquan, LI Qing
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Function-call Instruction Characteristic Analysis Based Instruction Set Architecture Recognization Method for Firmwares [PDF]
Jisuanji kexueThe recognition of instruction set architecture is a crucial task for conducting security research on embedded devices,and has significant implications.However,existing studies and tools often suffer from low recognition accuracy and high false positive ...
JIA Fan, YIN Xiaokang, GAI Xianzhe, CAI Ruijie, LIU Shengli
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Instruction-Set Accelerated Implementation of CRYSTALS-Kyber
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2021 Large scale quantum computers will break classical public-key cryptography protocols by quantum algorithms such as Shor’s algorithm. Hence, designing quantum-safe cryptosystems to replace current classical algorithms is crucial.
Mojtaba Bisheh-Niasar +2 more
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