Results 41 to 50 of about 298,312 (311)
A Single Instruction Multiple Data Vectorization Reduction Method [PDF]
Jisuanji gongcheng, 2017 Single Instruction Multiple Data(SIMD) aims at exploiting the data-level parallelism of multimedia and scientific calculation.The true dependence caused by reduction operation hinders exploring data-level parallelism.But different architecture and ...
HAN Lin,GAO Wei,WANG Dong,WANG Pengxiang,LI Yingying
doaj +1 more source
General Architecture and Instruction Set Enhancements for Multimedia Applications [PDF]
Journal of Systemics, Cybernetics and Informatics, 2007 The present day multimedia applications (MMAs) are driving the computing industry as every application being developed is using multimedia in one or the other way.
Mansour Assaf, Aparna Rajesh
doaj
Abstract Stobjs and Their Application to ISA Modeling [PDF]
Electronic Proceedings in Theoretical Computer Science, 2013 We introduce a new ACL2 feature, the abstract stobj, and show how to apply it to modeling the instruction set architecture of a microprocessor. Benefits of abstract stobjs over traditional ("concrete'') stobjs can include faster execution, support for ...
Shilpi Goel +2 more
doaj +1 more source
MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches [PDF]
, 2011 SBST (Software Based Self-Testing) is an effective solution for in-system testing of SoCs without any additional hardware requirement. SBST is particularly suited for embedded blocks with limited accessibility, such as cache memories.
Di Carlo, Stefano +4 more
core +1 more source
Adding 32-bit Mode to the ACL2 Model of the x86 ISA [PDF]
Electronic Proceedings in Theoretical Computer Science, 2018 The ACL2 model of the x86 Instruction Set Architecture was built for the 64-bit mode of operation of the processor. This paper reports on our work to extend the model with support for 32-bit mode, recounting the salient aspects of this activity and ...
Alessandro Coglio, Shilpi Goel
doaj +1 more source
Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture
IEEE Access, 2017 Single-instruction set architecture (ISA) heterogeneous multi-processor architecture is promising for developing multi-processor system-on-chips (MPSoCs). In this architecture, all processors execute the same instruction set, yet with various performance
Yi-Jung Chen +5 more
doaj +1 more source
A New Approach to Parallel Processing
IEEE Access, 2020 The Application Space Architecture (ASA) defines parallel processor design as an adjunct to the Instruction Set Architectures (ISA) defined by Von Neumann for single processors.
William C. Cave +5 more
doaj +1 more source
An Implementation of a Renesas H8/300 Microprocessor with a Cycle-Level Timing Extension [PDF]
, 2006 We describe an implementation of the Renesas H8/300 16-bit processor in VHDL suitable for synthesis on an FPGA. We extended the ISA slightly to accomodate cycle-accurate timers accessible from the instruction set, designed to provide more precise real ...
Coca, Javier +3 more
core +2 more sources
ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs
IEEE Open Journal of Circuits and Systems, 2021 ConvAix is an application-specific instruction-set processor (ASIP) that enables the energy-efficient processing of convolutional neural networks (CNNs) while retaining substantial flexibility through its instruction-set architecture (ISA) based design ...
Andreas Bytyn +2 more
doaj +1 more source
FEBS Letters, EarlyView.Bifidobacterium bifidum establishes symbiosis with infants by metabolizing lacto‐N‐biose I (LNB) from human milk oligosaccharides (HMOs). The extracellular multidomain enzyme LnbB drives this process, releasing LNB via its catalytic glycoside hydrolase family 20 (GH20) lacto‐N‐biosidase domain.
Xinzhe Zhang +5 more
wiley +1 more source