Results 51 to 60 of about 539,422 (337)
On-Line Instruction-checking in Pipelined Microprocessors [PDF]
, 2008 Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges.
Di Carlo, Stefano +2 more
core +2 more sources
Micromachines, 2021 Artificial intelligence (AI) has successfully made its way into contemporary industrial sectors such as automobiles, defense, industrial automation 4.0, healthcare technologies, agriculture, and many other domains because of its ability to act ...
Fatima Hameed Khan +2 more
doaj +1 more source
A complete formal semantics of x86-64 user-level instruction set architecture
ACM-SIGPLAN Symposium on Programming Language Design and Implementation, 2019 We present the most complete and thoroughly tested formal semantics of x86-64 to date. Our semantics faithfully formalizes all the non-deprecated, sequential user-level instructions of the x86-64 Haswell instruction set architecture.
Sandeep Dasgupta +4 more
semanticscholar +1 more source
Machine Assisted Proof of ARMv7 Instruction Level Isolation Properties [PDF]
, 2013 In this paper, we formally verify security properties of the ARMv7 Instruction Set Architecture (ISA) for user mode executions. To obtain guarantees that arbitrary (and unknown) user processes are able to run isolated from privileged software and other ...
A. Fox +6 more
core +2 more sources
Design modified architecture for MCS-51 with innovated instructions based on VHDL
Ain Shams Engineering Journal, 2013 This paper introduces two new complex instructions over the application with specific instruction set processor. For the MCS-51 family, utilizing a reserved bit, and the unused machine code “A5h” we can modify the conventional instruction set ...
Abd-Elmoneim Mohamed Fouda +1 more
doaj +1 more source
Automatic C Compiler Generation from Architecture Description Language ISAC [PDF]
, 2011 This paper deals with retargetable compiler generation. After an introduction to application-specific instruction set processor design and a review of code generation in compiler backends, ISAC architecture description language is introduced.
Hranac, Jan +4 more
core +1 more source
Comprehensive Review of Research on Dynamic Binary Translation Techniques [PDF]
Jisuanji kexue yu tansuoSolving compatibility issues in programs is crucial for building a domestic software ecosystem. With the diversification of computer architectures, ensuring software runs smoothly across different platforms and hardware environments has become an urgent ...
ZHANG Jin, SHAN Zehu, LIU Xiaodong, WANG Wenzhu, YU Jie, PENG Long, XIE Qiyou
doaj +1 more source
IET Information Security, 2022 A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still be ...
Yuze Wang, Peng Liu, Yingtao Jiang
doaj +1 more source
MOM: a matrix SIMD instruction set architecture for multimedia applications [PDF]
, 1999 MOM is a novel matrix-oriented ISA paradigm for multimedia applications, based on fusing conventional vector ISAs with SIMD ISAs such as MMX. This paper justifies why MOM is a suitable alternative for the multimedia domain due to its efficiency handling ...
Corbal San Adrián, Jesús +2 more
core +1 more source
Addressing Mode Extension to the ARM/Thumb Architecture
Advances in Electrical and Computer Engineering, 2014 In this paper, two new addressing modes are introduced to the 16-bit Thumb instruction set architecture to improve performance of the ARM/Thumb processors.
KIM, D.-H.
doaj +1 more source