Results 61 to 70 of about 539,422 (337)
Research on LLM Vector Dot Product Acceleration Based on RISC-V Matrix Instruction Set Extension [PDF]
Jisuanji kexueConsidering the high-performance and low-power requirements of edge AI,this paper designs a specialized instruction set processor for edge AI based on the RISC-V instruction set architecture,addressing practical issues in digital signal processing for ...
CHEN Xuhao, HU Sipeng, LIU Hongchao, LIU Boran, TANG Dan, ZHAO Di
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A Highly-Efficient and Tightly-Connected Many-Core Overlay Architecture
IEEE Access, 2021 The technology advances of CPU (Central Processing Unit) architecture alternate between generalization and specialization. In the past decade, the general performance has been enhanced while addressing the new brick walls that include power, memory, and ...
Riadh Ben Abdelhamid +2 more
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Analysis on the Possibility of RISC-V Adoption [PDF]
, 2020 As the interface between hardware and software, Instruction Set Architectures (ISAs) play a key role in the operation of computers. While both hardware and software have continued to evolve rapidly over time, ISAs have undergone minimal change. Since its
Scott, Ian
core
Abstract Stobjs and Their Application to ISA Modeling [PDF]
Electronic Proceedings in Theoretical Computer Science, 2013 We introduce a new ACL2 feature, the abstract stobj, and show how to apply it to modeling the instruction set architecture of a microprocessor. Benefits of abstract stobjs over traditional ("concrete'') stobjs can include faster execution, support for ...
Shilpi Goel +2 more
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Adding 32-bit Mode to the ACL2 Model of the x86 ISA [PDF]
Electronic Proceedings in Theoretical Computer Science, 2018 The ACL2 model of the x86 Instruction Set Architecture was built for the 64-bit mode of operation of the processor. This paper reports on our work to extend the model with support for 32-bit mode, recounting the salient aspects of this activity and ...
Alessandro Coglio, Shilpi Goel
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BPFabric: Data Plane Programmability for Software Defined Networks [PDF]
, 2017 In its current form, OpenFlow, the de facto implementation of SDN, separates the network’s control and data planes allowing a central controller to alter the matchaction pipeline using a limited set of fields and actions.
Jouet, Simon, Pezaros, Dimitrios P.
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General Architecture and Instruction Set Enhancements for Multimedia Applications [PDF]
Journal of Systemics, Cybernetics and Informatics, 2007 The present day multimedia applications (MMAs) are driving the computing industry as every application being developed is using multimedia in one or the other way.
Mansour Assaf, Aparna Rajesh
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MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches [PDF]
, 2011 SBST (Software Based Self-Testing) is an effective solution for in-system testing of SoCs without any additional hardware requirement. SBST is particularly suited for embedded blocks with limited accessibility, such as cache memories.
Di Carlo, Stefano +4 more
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Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture
IEEE Access, 2017 Single-instruction set architecture (ISA) heterogeneous multi-processor architecture is promising for developing multi-processor system-on-chips (MPSoCs). In this architecture, all processors execute the same instruction set, yet with various performance
Yi-Jung Chen +5 more
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ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs
IEEE Open Journal of Circuits and Systems, 2021 ConvAix is an application-specific instruction-set processor (ASIP) that enables the energy-efficient processing of convolutional neural networks (CNNs) while retaining substantial flexibility through its instruction-set architecture (ISA) based design ...
Andreas Bytyn +2 more
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