Results 71 to 80 of about 539,422 (337)
A New Approach to Parallel Processing
IEEE Access, 2020 The Application Space Architecture (ASA) defines parallel processor design as an adjunct to the Instruction Set Architectures (ISA) defined by Von Neumann for single processors.
William C. Cave +5 more
doaj +1 more source
An Implementation of a Renesas H8/300 Microprocessor with a Cycle-Level Timing Extension [PDF]
, 2006 We describe an implementation of the Renesas H8/300 16-bit processor in VHDL suitable for synthesis on an FPGA. We extended the ISA slightly to accomodate cycle-accurate timers accessible from the instruction set, designed to provide more precise real ...
Coca, Javier +3 more
core +2 more sources
FEBS Letters, EarlyView.Exposure to common noxious agents (1), including allergens, pollutants, and micro‐nanoplastics, can cause epithelial barrier damage (2) in our body's protective linings. This may trigger an immune response to our microbiome (3). The epithelial barrier theory explains how this process can lead to chronic noncommunicable diseases (4) affecting organs ...
Can Zeyneloglu +17 more
wiley +1 more source
Janus: An Uncertain Cache Architecture to Cope with Side Channel Attacks
, 2017 Side channel attacks are a major class of attacks to crypto-systems. Attackers collect and analyze timing behavior, I/O data, or power consumption in these systems to undermine their effectiveness in protecting sensitive information.
Darabi, Mostafa +4 more
core +1 more source
Automatic Generation of Interpreter for Multilingual Virtual Machine
Современные информационные технологии и IT-образование, 2021 The article says about existing implementations of interpreter generators and proposes an approach for generating interpreters in assembly for several architectures by describing a set of instructions (BISA - Bytecode Instruction Set Architecture) of a ...
Mark Gonopolskiy
doaj +1 more source
FEBS Letters, EarlyView.The Arabidopsis mutants hls1 hlh1 and amp1 lamp1 exhibit pleiotropic developmental phenotypes. Although the functions of the causative genes remain unclear, they act in the same genetic pathway and are thought to generate non‐cell‐autonomous signals.
Takashi Nobusawa, Makoto Kusaba
wiley +1 more source
FEBS Letters, EarlyView.Phytohormone brassinosteroid‐induced gene regulation by the transcription factor BIL1/BZR1 involves redox‐dependent DNA‐binding alternation and interaction with the transcription factor PIF4. The reduced BIL1/BZR1 dimer binds preferred cis‐elements, while oxidation alters its oligomerization state and disrupts DNA‐binding ability.
Shohei Nosaki +4 more
wiley +1 more source
Graphic Library Optimization for MIPS Architecture
Elektronika ir Elektrotechnika, 2020 The aim of this paper and research was to analyse the efficiency of the compiler-generated code for the graphics library and to present results obtained by optimization for the MIPS (Million Instructions Per Second) architecture.
Teodora Novkovic +3 more
doaj +1 more source
High performance extendable instruction set computing [PDF]
, 2001 In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems.
Appelbe, W, Beckett, P, Lee, H
core
Late allocation and early release of physical registers [PDF]
, 2004 The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the ...
González Colás, Antonio María +4 more
core +2 more sources