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Proceedings of the May 6-10, 1974, national computer conference and exposition on - AFIPS '74, 1974
As the level of complexity of digital systems increases, the problem of interconnecting subunits is receiving increasing attention. We are reaching the point where processing speed cannot be further improved through the use of faster componentry. Further speed-up of systems will most likely result from changes in the organization and structure of ...
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As the level of complexity of digital systems increases, the problem of interconnecting subunits is receiving increasing attention. We are reaching the point where processing speed cannot be further improved through the use of faster componentry. Further speed-up of systems will most likely result from changes in the organization and structure of ...
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Reconfiguration Algorithms for Interconnection Networks
IEEE Transactions on Computers, 1985The correspondence examines the functional relations within a class of multistage interconnection networks. It is known that these networks are not rearrangeable. This fact has led to some research on interconnection network relations. The correspondence deals with one aspect of this research, namely, that of constructing an equivalence map between two
A. Yavuz Oruç +2 more
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Optical Interconnects for Network on Chip
2006 1st International Conference on Nano-Networks and Workshops, 2006This paper resumes some state-of-the-art results of research in view of the realization of optical interconnects as physical link for Network on Chip (NoC). Emphasis is given in particular to amorphous Silicon technology for its actual technological compatibility with CMOS microchips.
Scandurra A. +4 more
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The Reverse-Exchange Interconnection Network
IEEE Transactions on Computers, 1980Properties of the reverse-exchange interconnection network are used to develop a reconfiguration scheme and a two-pass structure for enhancing the efficiency of a class of multistage interconnection networks. Functional relationships among a class of multistage interconnection networks are first derived.
Chuan-lin Wu, Tse-Yun Feng
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On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers, 1980A baseline network and a configuration concept are introduced to evaluate relationships among some proposed multistage interconnection networks. It is proven that the data manipulator (modified version), flip network, omega network, indirect binary n-cube network, and regular SW banyan network (S = F = 2) are topologically equivalent. The configuration
Chuan-lin Wu, Tse-Yun Feng
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Comparing interconnection networks
2005We review results on embedding network and program structures into popular parallel computer structures. Such embeddings can be viewed as high level descriptions of efficient methods to simulate an algorithm designed for one type of architecture on a different network structure and/or techniques to distribute data/program variables to achieve optimum ...
Burkhard Monien, Ivan Hal Sudborough
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Interconnection of computer networks
Computer Networks (1976), 1977Abstract As computer networks proliferate, interest in interconnecting networks will increase. This paper considers the problems of interconnecting heterogeneous computer networks to provide communication between processes in different networks. The treatment is tutorial with a comprehensive survey of relevant work.
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THE CUBE-OF-RINGS INTERCONNECTION NETWORK
International Journal of Foundations of Computer Science, 1998We present a family of interconnection networks named the Cube-Of-Rings (COR) networks along with their basic graph-theoretic properties. Aspects of group graph theory are used to show the COR networks are symmetric and optimally fault tolerant. We present a closed-form expression of the diameter and optimal one-to-one routing algorithm for any member
Thomas J. Cortina, Zhiwei Xu
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BROADCASTING IN BUS INTERCONNECTION NETWORKS
Journal of Interconnection Networks, 1994In most distributed memory MIMD multiprocessors, processors are connected by a point-to-point interconnection network, usually modeled by a graph where processors are nodes and communication links are edges. Since interprocessor communication frequently constitutes serious bottlenecks, several architectures were proposed that enhance point-to-point ...
Afonso Ferreira +2 more
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Mapping interconnection networks into VEDIC networks
[1993] Proceedings Seventh International Parallel Processing Symposium, 2002The authors show the universality of the VEDIC network in simulating other well known interconnection networks by generating the parameters of the VEDIC network automatically. Algorithms are given to represent chordal rings, toroidal meshes, binary hypercubes, k-ary n-cubes, and Cayley graphs-star graph and pancake graph, as VEDIC networks. Using these
Vipin Chaudhary +2 more
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