Results 221 to 230 of about 360,003 (358)
FFO-based controller for 3-phase inverter to reduce power quality problems in PV-integrated microgrid system. [PDF]
Kumar NA +4 more
europepmc +1 more source
The integration of photovoltaic (PV) systems into building structures introduces distinct fire risks with critical implications for occupant safety. This review examines the key fire hazards associated with PV implementation and explores mitigation strategies, including flame‐retardant additives.
Florian Ollagnon +7 more
wiley +1 more source
Fast Growth of Centimeter-Scale Molybdenum Disulfide Single Crystal for Energy-Efficient Logic Circuits. [PDF]
Zheng B +15 more
europepmc +1 more source
Substrate Stress Relaxation Regulates Cell‐Mediated Assembly of Extracellular Matrix
Silicone‐based viscoelastic substrates with tunable stress relaxation reveal how matrix mechanics regulates cellular mechanosensing and cell‐mediated matrix remodelling in the stiff regime. High stress relaxation promotes assembly of fibronectin fibril‐like structures, increased nuclear localization of YAP and formation of β1 integrin‐enriched ...
Jonah L. Voigt +2 more
wiley +1 more source
Designing of Inverted F Antenna and Utilizing of Blockchain in Vehicle Systems
Raed S. M. Daraghma +3 more
openalex +1 more source
Power quality optimization framework for three phase microgrids with grid tied solar PV and battery storage under nonlinear loads. [PDF]
Saleh Waseem Abbasi M +5 more
europepmc +1 more source
Shellac, a centuries‐old natural resin, is reimagined as a green material for flexible electronics. When combined with silver nanowires, shellac films deliver transparency, conductivity, and stability against humidity. These results position shellac as a sustainable alternative to synthetic polymers for transparent conductors in next‐generation ...
Rahaf Nafez Hussein +4 more
wiley +1 more source
Weak Invertibility of Finite Automata and Cryptanalysis on FAPKC [PDF]
Zong Duo Dai +2 more
openalex +1 more source
Low power and high-speed quadrate node upset tolerant latch design using CNTFET. [PDF]
Asiya S, S SK.
europepmc +1 more source

