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Networks, 1978
AbstractThe problems of layout of printed circuits and large scale integrated chips are very complex and are therefore usually approached by heuristic methods.This paper presents a more analytic approach to an elementary subset of these problems, using combinatorial and graphtheoretic arguments.
M. Cutler, Yossi Shiloach
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AbstractThe problems of layout of printed circuits and large scale integrated chips are very complex and are therefore usually approached by heuristic methods.This paper presents a more analytic approach to an elementary subset of these problems, using combinatorial and graphtheoretic arguments.
M. Cutler, Yossi Shiloach
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2011 IEEE 52nd Annual Symposium on Foundations of Computer Science, 2011
Consider the problem of laying out a set of $n$ images that match a query onto the nodes of a $\sqrt{n}\times\sqrt{n}$ grid. We are given a score for each image, as well as the distribution of patterns by which a user's eye scans the nodes of the grid and we wish to maximize the expected total score of images selected by the user.
CHIERICHETTI, FLAVIO +2 more
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Consider the problem of laying out a set of $n$ images that match a query onto the nodes of a $\sqrt{n}\times\sqrt{n}$ grid. We are given a score for each image, as well as the distribution of patterns by which a user's eye scans the nodes of the grid and we wish to maximize the expected total score of images selected by the user.
CHIERICHETTI, FLAVIO +2 more
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The layout synthesizer: an automatic Netlist-to-Layout system
Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989A system generating compacted physical layouts from MOS transistor netlists has been developed. It uses a novel graph-theoretical placement algorithm to simultaneously maximize diffusion sharing and minimize the wiring area. The algorithm is not limited to circuits that have equal numbers of NMOS and PMOS transistors.
C. C. Chen, S.-L. Chow
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IEEE Symposium on Information Visualization, 2005. INFOVIS 2005., 2005
Cartographers have long used flow maps to show the movement of objects from one location to another, such as the number of people in a migration, the amount of goods being traded, or the number of packets in a network. The advantage of flow maps is that they reduce visual clutter by merging edges.
Doantam Phan +4 more
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Cartographers have long used flow maps to show the movement of objects from one location to another, such as the number of people in a migration, the amount of goods being traded, or the number of packets in a network. The advantage of flow maps is that they reduce visual clutter by merging edges.
Doantam Phan +4 more
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IEEE Transactions on Visualization and Computer Graphics, 2011
We introduce hi-trees, a new visual representation for hierarchical data in which, depending on the kind of parent node, the child relationship is represented using either containment or links. We give a drawing convention for hi-trees based on the standard layered drawing convention for rooted trees, then show how to extend standard bottom-up tree ...
Kim Marriott +4 more
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We introduce hi-trees, a new visual representation for hierarchical data in which, depending on the kind of parent node, the child relationship is represented using either containment or links. We give a drawing convention for hi-trees based on the standard layered drawing convention for rooted trees, then show how to extend standard bottom-up tree ...
Kim Marriott +4 more
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Layout and Post-layout Simulations
2015The layout of the QVCO buffer sub-system of Sect. 4.2 is discussed in this chapter. Post-layout simulation results are also provided.
Khaled Khalaf +3 more
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A Reduction of Grid-Bag Layout to Auckland Layout
2010 21st Australian Software Engineering Conference, 2010Many major programming platforms support layout managers in Grid-bag style, where GUI elements can be placed on a rectangular grid. In Grid-bag layout mangers, cells of the underlying grid can be merged in order to create more complex layouts. In this work we classify software engineering issues with Grid-bag layout managers - chiefly bad coupling and ...
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DFT Aware Layout - Layout Aware DFT
14th Asian Test Symposium (ATS'05), 2005The era of the SOC and sub 100nm process technologies has created several new sets of challenges for the test engineer. One of these is the return to prominence of the effect of test infrastructure on the overall physical design of the device. This time it is not impact of logic overhead which is at the top of the list but the need for DFT to interact ...
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CHI '10 Extended Abstracts on Human Factors in Computing Systems, 2010
The authors also describe a framework that enables the creation of a layout engine, which satisfies the user demands identified in a user study. The approach is capable of defining layout behavior for various visual languages like graphs, class diagrams, mindmaps, business process models, or even GUI forms.
Sonja Maier, Mark Minas
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The authors also describe a framework that enables the creation of a layout engine, which satisfies the user demands identified in a user study. The approach is capable of defining layout behavior for various visual languages like graphs, class diagrams, mindmaps, business process models, or even GUI forms.
Sonja Maier, Mark Minas
openaire +1 more source

