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End-Stage Renal Disease Treatment Choices Model and Use of Home Dialysis and Kidney Transplant.
JAMA Health ForumDixit MN +12 more
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2007 International Semiconductor Conference, 2007
The paper presents the main noise sources in CMOS low dropout linear voltage regulators (LDOs), their simulation and measurement. The paper is focused on noise performance, which is of great importance for the design of CMOS circuits.
Ovidiu Profirescu +2 more
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The paper presents the main noise sources in CMOS low dropout linear voltage regulators (LDOs), their simulation and measurement. The paper is focused on noise performance, which is of great importance for the design of CMOS circuits.
Ovidiu Profirescu +2 more
openaire +1 more source
A Fully Integrated 1.2V LDO Regulator
2020 32nd International Conference on Microelectronics (ICM), 2020This work presents a fully integrated low-drop out voltage regulator that achieves a fast-transient response by utilizing two feedback mechanisms. The first feedback mechanism is an analog regulation that includes an error amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators ...
Khaldoon Abugharbieh +2 more
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Novel current limit circuitry for LDOs
IEEE EUROCON 2017 -17th International Conference on Smart Technologies, 2017This paper presents a novel circuit implementation for overcurrent protection of low-dropout voltage regulators, that is able to limit the maximum current the regulator can source into the load to a value set by the user and to keep the current limit value fairly independent of process variation and output voltage, as well as maintaining its ...
Cosmin-Sorin Plesa +3 more
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On design of memory retention LDO regulator
2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016The paper describes operation and design of a memory retention LDO regulator. The LDO regulator is operating in a very wide range of the output currents (up to 100 uA) with a very small quiescent current (in the range of 100–300 nA). In the proposed circuit this range is achieved using a nonlinear translinear cell added to the the unity gain stage ...
Igor M. Filanovsky +2 more
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LAAEM: A Method to Enhance LDoS Attack
IEEE Communications Letters, 2016Based on LDoS, we propose bots multiplexing in multitargets attack scenario, and then present the LDoS attack ability enhancing method. In simulation, the method shows good performance and adaptability, it can enhance attack ability effectively under variety of correlated parameters.
Heshuai Li +5 more
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Chaos-based detection of LDoS attacks
Journal of Systems and Software, 2013A low-rate denial of service (LDoS) attack behaves as a small signal in periodic pulses with low average rate, which hides in normal TCP traffic stealthily. LDoS attacks reduce link throughput and degrade QoS of a target. An approach of detecting LDoS attacks is proposed based on Duffing oscillator in chaos systems. The approach detects LDoS attacks by
Zhijun Wu 0001 +4 more
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Time-based Digital LDO Regulator
2019 31st International Conference on Microelectronics (ICM), 2019This paper presents a digital LDO (DLDO) regulator utilizing a time-based comparator rather than a voltage-based comparator in order to exploit the advantages of time domain and produce a more robust regulator. The time-based comparator compares between the reference and the load voltage levels and generates a digital bit that turns on/off the PMOS ...
Leen Qasem +3 more
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2013
A 1.2 V 40 mA low-dropout regulator (LDO) for system-on-chip applications with 700 mV dropout is designed in Verilog-A. The proposed LDO provides fast line and load-transient responses with temperature-independent operation. The proposed LDO has been designed in Verilog-A using tsmc 65 nm CMOS technology and the total error of the output voltage due to
Raveendra Somana +2 more
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A 1.2 V 40 mA low-dropout regulator (LDO) for system-on-chip applications with 700 mV dropout is designed in Verilog-A. The proposed LDO provides fast line and load-transient responses with temperature-independent operation. The proposed LDO has been designed in Verilog-A using tsmc 65 nm CMOS technology and the total error of the output voltage due to
Raveendra Somana +2 more
openaire +1 more source
Design of an LDO with capacitor multiplier
Journal of Semiconductors, 2010This paper presents a low quiescent current, highly stable low-drop out (LDO) regulator. In order to reduce capacitor value and control frequency response peak, capacitor multipliers are adopted in the compensation circuit with mathematic calculations. The phase margin is adequate when the load current is 0.1 or 150 mA.
Ying Jianhua, Huang Meng, Huang Yang
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