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The Ninth International Conference onCommunications Systems, 2004. ICCS 2004., 2004
Low-density parity-check (LDPC) codes are well known for their abilities to achieve near Shannon channel capacity limit and low decoding complexity compared with the turbo decoder. However, their encoding complexities grow with the square of the code length.
null Zhang Qi, null Ng Chun Sum
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Low-density parity-check (LDPC) codes are well known for their abilities to achieve near Shannon channel capacity limit and low decoding complexity compared with the turbo decoder. However, their encoding complexities grow with the square of the code length.
null Zhang Qi, null Ng Chun Sum
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Proceedings of the 46th Annual Design Automation Conference, 2009
This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a ...
Erick Amador +2 more
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This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a ...
Erick Amador +2 more
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2006 8th international Conference on Signal Processing, 2006
The presented LDPC-codec has no encrypting function since its rediscovering, and the presented encrypting for signal transmission needs additional algorithm and program, which leads the great time delay for the signal receiving. This paper reveals that LDPC-codec itself can have the desired encrypting faction if adopting our processing approach for the
Yang Xiao, Ying Zhao, Moon Lee
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The presented LDPC-codec has no encrypting function since its rediscovering, and the presented encrypting for signal transmission needs additional algorithm and program, which leads the great time delay for the signal receiving. This paper reveals that LDPC-codec itself can have the desired encrypting faction if adopting our processing approach for the
Yang Xiao, Ying Zhao, Moon Lee
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Protograph-based LDPC-Hadamard Codes
2020 IEEE Wireless Communications and Networking Conference (WCNC), 2020In this paper, we propose a new method to design low-density parity-check Hadamard (LDPC-Hadamard) codes — a type of ultimate-Shannon-limit approaching channel codes. The technique is based on applying Hadamard constraints to the check nodes in a generalized protograph-based LDPC code, followed by lifting the generalized protograph.
Peng-Wei Zhang +2 more
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Nonbinary LDPC-Coded Spatial Modulation
IEEE Transactions on Wireless Communications, 2017This paper presents a nonbinary low-density parity-check (LDPC) coded spatial modulation (CSM) for multiple-input multiple-output communication systems, in which the information bits for choosing active transmit antennas and the bits for choosing constellation signals are protected by a nonbinary LDPC code.
Dan Feng +3 more
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Integrated Design of JSCC Scheme Based on Double Protograph LDPC Codes System
IEEE Communications Letters, 2019In this letter, an integrated design of joint source-channel coding scheme based on the double protograph low-density parity-check (DP-LDPC) codes is proposed.
Qiwang Chen +3 more
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A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2019In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently.
Yen-Chin Liao +3 more
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Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC Reading
Design Automation Conference, 2019Existing studies have uncovered that there exist significant Raw Bit Error Rates (RBERs) variations among different layers of 3D flash memories due to manufacture process variation.
Yajuan Du +4 more
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Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019By storing multibit per cell, multilevel cell (MLC) NAND flash memory achieves high storage capacity, but sacrificing data reliability. Error correction codes, such as Bose–Chaudhuri–Hocquenghem (BCH) codes, are widely used to ensure data reliability ...
Meng Zhang +4 more
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An LDPC decoder architecture for multi-rate QC-LDPC codes
2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011This paper presents a partially parallel LDPC decoder architecture for QC-LDPC codes. In particular, we introduce a check node processing element which is 3-parallel, adjustable to irregular inputs and easily expandable. Furthermore, our decoder is applicable to multi-rate system by simply writing additional data to internal RAM.
Sung-Woo Choi +2 more
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