Results 161 to 170 of about 788 (196)

Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST

2009 IEEE International Advance Computing Conference, 2009
This paper proposes a low power Linear Feedback Shift Register (LFSR) for Test Pattern Generation (TPG) technique with reducing power dissipation during testing. The correlations between the consecutive patterns are higher during normal mode than during testing.
Balwinder Singh
exaly   +2 more sources

Condensed Linear Feedback Shift Register (LFSR) Testing—A Pseudoexhaustive Test Technique

IEEE Transactions on Computers, 1986
This paper presents a design technique for linear feedback shift registers that generate test patterns for pseudoexhaustive testing. This technique is applicable to any combinational network in which none of the outputs depends on all inputs. It does not rewire the original network inputs during in-circuit test pattern generation. Thus, the possibility
Laung-Terng Wang
exaly   +2 more sources

Design of lfsr (linear feedback shift register) for low power test pattern generator

2017 International Conference on Networks & Advances in Computational Technologies (NetACT), 2017
VLSI primary demanding sectors are power, area and performance. The portable device implications are expanding quickly. So circuits should be intended for low power dispersal. Dissipation of power is getting higher in test mode than at typical mode. Subsequently, power optimization at testing is essential angle.
R. Saraswathi, R. Manikandan
exaly   +2 more sources

WEP implementation using Linear Feedback Shift Register (LFSR) and dynamic key

2011 2nd International Conference on Computer and Communication Technology (ICCCT-2011), 2011
The WEP (wired equivalent privacy) is an IEEE 802.11's optional stream cipher scheme implemented in its MAC layer for confidentiality of the data frames. It uses RC4 for pn-sequence generation and the same is xored with the plain text and added integrity check value produced by the CRC-32.
G P Biswas
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High speed VLSI architecture for general linear feedback shift register (LFSR) structures

2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers, 2009
Based on previous three-step high-speed VLSI architecture for LFSR structures, this paper proposes an improved three-step LFSR architecture with both higher hardware efficiency and speed. Generator polynomials for the first and third steps are constructed with iterative small length polynomials, which can in turn be easily handled by proposed look ...
Keshab K Parhi
exaly   +2 more sources

A review on power optimization of linear feedback shift register (LFSR) for Low power built in self test (BIST)

2011 3rd International Conference on Electronics Computer Technology, 2011
A new low transition test pattern generator using a linear feedback shift register (LFSR) called LT-LFSR reduce the average and peak power of a circuit during test by generating three intermediate patterns between the random patterns. The goal of having intermediate patterns is to reduce the transitional activities of Primary Inputs (PI) which ...
K Ragini
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FT-LFSR: A Fault Tolerant Architecture for Linear Feedback Shift Registers

2021 26th International Computer Conference, Computer Society of Iran (CSICC), 2021
Linear Feedback Shift Registers (LFSR) are extensively used in variety of applications such as Built-In-Self-Test circuits or Pseudo Random Number Generators. Hence, fault tolerant design of LFSR is essential for the applications with high reliability demands.
Mohammad Zaree, Mohsen Raji
openaire   +1 more source

Double Fold Encryption Algorithm Using Adjacency Matrix and Linear Feedback Shift Register (LFSR) as Diffusion

2022
exaly   +2 more sources