Results 71 to 80 of about 10,440 (199)
Two-stage compilation for optimizing and deploying programs in general purpose languages
Труды Института системного программирования РАН, 2018 We describe the approach for two-stage compilation of C/C++ programs using the LLVM compiler infrastructure that allows optimizing programs taking into account the user profile and his/her target machine features, as well as deploying programs in a cloud
Arutyun Avetisyan
doaj
Machine Learning-Based Vulnerability Detection in Rust Code Using LLVM IR and Transformer Model
Machine Learning and Knowledge ExtractionRust’s growing popularity in high-integrity systems requires automated vulnerability detection in order to maintain its strong safety guarantees. Although Rust’s ownership model and compile-time checks prevent many errors, sometimes unexpected bugs may ...
Young Lee +4 more
doaj +1 more source
Interprocedural taint analysis for LLVM-bitcode
Труды Института системного программирования РАН, 2018 Today the development cycle of many application classes requires a security analysis stage. Taint analysis is widely used to check programs for different security vulnerabilities.
V. K. Koshelev +2 more
doaj +1 more source
Refactoring to Standard C++20 Modules
Journal of Software: Evolution and Process, Volume 37, Issue 1, January 2025.This paper investigates a semi‐automatic modularization method to refactor existing C++ projects. Our approach uses dependency analysis and clustering to organize elements of projects into modules, without domain‐specific information. To fully facilitate the use of Modules, it is likely that both project‐internal and user‐facing interfaces must be ...
Richárd Szalay, Zoltán Porkoláb
wiley +1 more source
Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures
, 2018 An accurate prediction of scheduling and execution of instruction streams is a necessary prerequisite for predicting the in-core performance behavior of throughput-bound loop kernels on out-of-order processor architectures.
Hager, Georg +4 more
core +1 more source
Batched ranged random integer generation
Software: Practice and Experience, Volume 55, Issue 1, Page 155-169, January 2025.Summary Pseudorandom values are often generated as 64‐bit binary words. These random words need to be converted into ranged values without statistical bias. We present an efficient algorithm to generate multiple independent uniformly‐random bounded integers from a single uniformly‐random binary word, without any bias.
Nevin Brackett‐Rozinsky, Daniel Lemire
wiley +1 more source
IET Communications, Volume 19, Issue 1, January/December 2025.Abstract As organizations increasingly rely on network services, the prevalence and severity of Denial of Service (DoS) and Distributed Denial of Service (DDoS) attacks have emerged as significant threats. The cornerstone of effectively addressing these challenges lies in the timely and precise detection capabilities offered by advanced intrusion ...
Nemalikanti Anand +5 more
wiley +1 more source
, 2023 У роботі наведено огляд компонентів платформи LLVM, проаналізовано механізми безпеки та виконано тестування захищеностів від шкідливого коду. В аналіз безпеки входить перевірка можливих вразливостей, та систем захисту які інтегровані в системі.
openaire +1 more source
Cross‐Platform Based Scalable 3D Media Sequence Playback Framework Architecture
Electronics Letters, Volume 61, Issue 1, January/December 2025.This paper presents a novel study on a web playback framework designed to efficiently render stereoscopic 3D media content across various platforms within web environments. We propose a scalable 3D media web playback framework (S3WPF) that leverages advanced encoding technology.
Kwangmu Shin, Sunghoon Kim
wiley +1 more source
Ithemal: Accurate, Portable and Fast Basic Block Throughput Estimation using Deep Neural Networks
, 2019 Predicting the number of clock cycles a processor takes to execute a block of assembly instructions in steady state (the throughput) is important for both compiler designers and performance engineers.
Amarasinghe, Saman +3 more
core