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Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory, 2001We design low-density parity-check (LDPC) codes that perform at rates extremely close to the Shannon capacity. The codes are built from highly irregular bipartite graphs with carefully chosen degree patterns on both sides. Our theoretical analysis of the
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IEEE Transactions on Information Theory, 2001We present a general method for determining the capacity of low-density parity-check (LDPC) codes under message-passing decoding when used over any binary-input memoryless channel with discrete or continuous output alphabets.
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A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder
Proceedings of the IEEE Custom Integrated Circuits Conference, 2001A 1024 bit rate-1/2 Low Density Parity Check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The parallel decoder architecture supports throughputs up to 1 Gb/s and convergence in the decoding algorithm ...
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