Peak Detector Effect in Low-Dropout Regulators [PDF]
IEEE Transactions on Nuclear Science, 2013 The peak detector effect is a phenomenon that makes single event transients much longer once an error amplifier switches from linear to saturation zone due to the presence of external capacitors. This is so-called since it was discovered in a simple voltage reference in which a parasitic lossy peak detector was unwillingly built in the output stage. In
Palomar Trives, Carlos +4 more
openaire +3 more sources
A 0.6 VIN 100 mV Dropout Capacitor-Less LDO with 220 nA IQ for Energy Harvesting System
Micromachines, 2023 A fully integrated and high-efficiency low-dropout regulator (LDO) with 100 mV dropout voltage and nA-level quiescent current for energy harvesting has been proposed and simulated in the 180 nm CMOS process in this paper.
Yuting Zhang, Qianhui Ge, Yanhan Zeng
doaj +1 more source
On and Off Chip Capacitor Free, Fast Response, Low Drop-out Voltage Regulator [PDF]
International Journal of Electronics and Telecommunications, 2019 A low drop-out [LDO] voltage regulator with fast transient response which does not require a capacitor for proper operation is proposed in this paper. Recent cap-less LDOs do not use off chip capacitor but instead they use on chip capacitor which occupy ...
Guruprasad, Kumara Shama
doaj +1 more source
Architectural Advancement of Digital Low-Dropout Regulators [PDF]
IEEE Access, 2020 Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-grained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks.
Muhammad Abrar Akram +2 more
openaire +2 more sources
Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique
IEEE Access, 2021 This paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output ...
Muhammad Asif +6 more
doaj +1 more source
Linear-assisted DC/DC converters with modified current-mode control applied to photovoltaic solar systems [PDF]
, 2014 This article shows the proposal of a current-mode one-cycle control for linear-assisted DC/DC converters. Linearassisted DC/DC converters are structures that allow to take advantages of the two classic alternatives in the design of power supply systems ...
Martínez García, Herminio
core +3 more sources
An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control
Energies, 2023 Digital low-dropout (DLDO) is widely used for power management in the system-on-chip (SoC) because of its low-voltage operation and process scalability.
Yen-Ming Chen, Ching-Jan Chen
doaj +1 more source
Supercapacitor assisted LDO (SCALDO) techniquean extra low frequency design approach to high efficiency DC-DC converters and how it compares with the classical switched capacitor converters [PDF]
, 2013 Supercapacitor assisted low dropout regulators (SCALDO) were proposed as an alternative design approach to DC-DC converters, where the supercapacitor circulation frequency (switching frequency) is in the order of few Hz to few 10s of Hz, with an output ...
Kankanamge, Kosala, Kularatna, Nihal
core +3 more sources
An Output Capacitor-Less Low-Dropout Regulator with 0–100 mA Wide Load Current Range
Energies, 2019 An output capacitor-less low-dropout (OCL-LDO) regulator with a wide range of load currents is proposed in this study. The structure of the proposed regulator is based on the flipped-voltage-follower LDO regulator.
Jihoon Park +4 more
doaj +1 more source
PSRR-enhanced low-dropout regulator
Electronics Letters, 2011 A power supply rejection ratio (PSRR) enhancement technique for the low-dropout regulator (LDR) is presented. This proposed LDR with a bandgap reference has been fabricated in a 0.35 µm CMOS process, and its active chip area is 0.1978 mm2. From experimental results, the proposed LDR provides a stable output voltage without the output capacitor and ...
W.-J. Huang, S.-I. Liu
openaire +1 more source