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Design for Testability of Low Dropout Regulators
2021 IEEE 39th VLSI Test Symposium (VTS), 2021Integrated LDOs are closed loop systems; characterization of their gain and bandwidth is critical. Generally, gain and bandwidth parameters are extracted from LDO design simulations. However, LDO loop parameter testing requires breaking the loop and injecting a test signal into the IC.
Anurag Tulsiram, William R. Eisenstadt
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Low-Dropout Voltage Source: An Alternative Approach for Low-Dropout Voltage Regulators
IEEE Transactions on Circuits and Systems II: Express Briefs, 2014In this brief, a high-order temperature-compensated 0.6-V low-dropout voltage source (LDVS) is realized in standard 0.13- $\mu\hbox{m}$ CMOS technology. The LDVS operates at supply voltages down to 0.75 V and consumes only 39 $\mu\hbox{A}$ while providing up to 100 mA of load current. Gate-to-channel capacitance values of MOSFETs are employed
Hamed Aminzadeh +2 more
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Recent Advances on Linear Low-Dropout Regulators
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021This brief revises the recent design trends of linear low-dropout regulators. The design issues and advantages of analog LDOs (ALDO) are discussed. High-performance operation and high rejection to supply noise when delivering large current values is a major advantage of the ALDO, but transient response when transitioning from standby operation to full ...
Jose Silva-Martinez +2 more
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Fractional Order Low–Dropout Voltage Regulator
2016 8th International Conference on Computational Intelligence and Communication Networks (CICN), 2016The Internet of Things offers tremendous potential to increasingly harness wireless and portable systems in everyday life. Low-dropout (LDO) linear regulators are essential components in numerous wireless and portable electronic devices and their performance in systems can be very important, given the need to power such devices particularly in ...
Sean Rocke, Craig Ramlal, Arvind Singh
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Design of a Low-Dropout Linear Regulator
2020 IEEE International Conference on Artificial Intelligence and Information Systems (ICAIIS), 2020This paper introduces a low-dropout linear regulator with an operating voltage of 2.5V. An anti-overshoot circuit is added to the error amplifier, and the regulator module is optimized based on circuit stability performance; Add trim function to feedback resistance network so that LDO can output different voltage values such as 1.1V, 1.8V and 2.2V ...
Enyu Xu, Xuehong He
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2015 IEEE Custom Integrated Circuits Conference (CICC), 2015
□ Output voltage generated using a resistive divider ▪ Fixed divide ratio -> sensitive to load current changes □ Feedback loop regulates R IN such that it is always a desired fraction of load current ▪ Output voltage is independent of load current.
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□ Output voltage generated using a resistive divider ▪ Fixed divide ratio -> sensitive to load current changes □ Feedback loop regulates R IN such that it is always a desired fraction of load current ▪ Output voltage is independent of load current.
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Low dropout voltage regulator for wireless applications
2002 IEEE 33rd Annual IEEE Power Electronics Specialists Conference. Proceedings (Cat. No.02CH37289), 2003Low dropout voltage regulators (LDO) are widely used in portable communication products such as cellular phones, pagers, and laptops. In this paper, we present a wide range load (100 mA) LDO designed with 0.25 /spl mu/m CMOS process. By using a fast transient loop, we obtained high performance in transient response and output stability.
null Shan Yuan, B.C. Kim
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A novel dual-feed low-dropout regulator
Journal of Semiconductors, 2015A novel dual-feed (DF) low-dropout (LDO) is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO.
Zhikui Duan +6 more
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A CMOS Low-Noise, Low-Dropout Regulator
2010 Asia-Pacific Power and Energy Engineering Conference, 2010This paper presents a design technique of low noise fully CMOS low-dropout voltage regulator based on suitable error amplifier and unity feedback network. The inherent thermal and flicker noise are represented by equivalent current and voltage sources.
Qingyun Li +5 more
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Analysis of low-dropout regulator topologies for low-voltage regulation
2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668), 2004The design considerations of integrated CMOS low-voltage low-dropout regulators are addressed in this paper. The limitations of a generic LDO based on dominant-pole compensation are discussed. Then, LDO with a voltage-buffer stage and the corresponding problems in low-voltage design are discussed.
null Sai Kit Lau +2 more
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