Results 301 to 310 of about 2,428,196 (357)
Some of the next articles are maybe not open access.
Proceedings of the 43rd Annual Symposium on Frequency Control, 2003
Low-power timekeeping methods have been developed that provide improved accuracy over the full military temperature range. These methods provide tradeoffs of accuracy vs. power consumption dependent upon the application. The system achieves this performance by using a microcomputer-compensated crystal oscillator (MCXO) to periodically update a low ...
M. Bloch +4 more
openaire +1 more source
Low-power timekeeping methods have been developed that provide improved accuracy over the full military temperature range. These methods provide tradeoffs of accuracy vs. power consumption dependent upon the application. The system achieves this performance by using a microcomputer-compensated crystal oscillator (MCXO) to periodically update a low ...
M. Bloch +4 more
openaire +1 more source
2016 29th IEEE International System-on-Chip Conference (SOCC), 2016
In the modern lower process node ASIC design the power is considered as the major factor. The low power design chips are required in many applications like mobile, computing, processing, and video and audio controller designs. Most of the SOC designs need the low power design support.
Sao-Jie Chen, Andrew Marshall
openaire +2 more sources
In the modern lower process node ASIC design the power is considered as the major factor. The low power design chips are required in many applications like mobile, computing, processing, and video and audio controller designs. Most of the SOC designs need the low power design support.
Sao-Jie Chen, Andrew Marshall
openaire +2 more sources
Low- Power Arithmetic Operators
2004After a short introduction to computer arithmetic, this presentation deals with hardware arithmetic operators optimized for low-power consumption. It presents addition algorithms, basic cells and optimizations techniques for low power. It also presents multiplication by constants, squaring and function approximations used in low-power operators ...
openaire +2 more sources
2013
This chapter presents architectural considerations for the proposed transceiver. Four main aspects are identified as essential for ultra-low power consumption. First, the definition of the receiver architecture is a fundamental issue as it affects the structure and design requirements of individual blocks.
Jens Masuch, Manuel Delgado-Restituto
openaire +1 more source
This chapter presents architectural considerations for the proposed transceiver. Four main aspects are identified as essential for ultra-low power consumption. First, the definition of the receiver architecture is a fundamental issue as it affects the structure and design requirements of individual blocks.
Jens Masuch, Manuel Delgado-Restituto
openaire +1 more source
2008 IEEE International Test Conference, 2008
The power consumed during test mode is higher than the functional mode and becomes significantly higher for low power devices. The increased heat can result in chip burnouts and reliability issues due to electro-migration. This poster presents the reasons for higher power consumption, its consequences, and various solutions, both at hardware and ...
S. Bahl, R. Sarkar, A. Garg
openaire +1 more source
The power consumed during test mode is higher than the functional mode and becomes significantly higher for low power devices. The increased heat can result in chip burnouts and reliability issues due to electro-migration. This poster presents the reasons for higher power consumption, its consequences, and various solutions, both at hardware and ...
S. Bahl, R. Sarkar, A. Garg
openaire +1 more source
Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08, 2008
Summary form only given. The fabless ASIC model has changed the landscape of ASIC design by offering a high-quality, cost-effective and open alternative to realizing ASICs. The very nature of this model (because of its reliance on the third-party foundry, IP ecosystem) offers unique challenges and opportunities for implementing low power chips.
Shashank Bhonge, Vamsi Boppana
openaire +1 more source
Summary form only given. The fabless ASIC model has changed the landscape of ASIC design by offering a high-quality, cost-effective and open alternative to realizing ASICs. The very nature of this model (because of its reliance on the third-party foundry, IP ecosystem) offers unique challenges and opportunities for implementing low power chips.
Shashank Bhonge, Vamsi Boppana
openaire +1 more source
IEEE Design & Test of Computers, 1994
Plans for a government sponsored research program call for the development of a new electronics technology base for hand-size information systems. This base will enable the design and implementation of semiconductor technologies that consume two orders of magnitude less power than conventional technology would have allowed.
Z.J. Lemnios, K.J. Gabriel
openaire +1 more source
Plans for a government sponsored research program call for the development of a new electronics technology base for hand-size information systems. This base will enable the design and implementation of semiconductor technologies that consume two orders of magnitude less power than conventional technology would have allowed.
Z.J. Lemnios, K.J. Gabriel
openaire +1 more source
On low power test and low power compression techniques
2018With the ever increasing integration capability of semiconductor technology, today’s large integrated circuits require an increasing amount of data to test them which increases test time and elevated requirements of tester memory. At the same time, as VLSI design sizes and their operating frequencies continue to increase, timing-related defects are ...
openaire +1 more source
2012
Dynamic random access memory (DRAM) is a volatile random access memory and the memory cell consists of a cell transistor and a capacitor [1–3], as shown in Fig. 5.1. The cell transistor is used to connect a storage node (N) and a data-line (DL) by activating a word-line (WL), while the capacitor, connected between N and the plate (PL), stores ...
openaire +1 more source
Dynamic random access memory (DRAM) is a volatile random access memory and the memory cell consists of a cell transistor and a capacitor [1–3], as shown in Fig. 5.1. The cell transistor is used to connect a storage node (N) and a data-line (DL) by activating a word-line (WL), while the capacitor, connected between N and the plate (PL), stores ...
openaire +1 more source