A Low-Dropout Regulator for SoC With $Q$-Reduction [PDF]
IEEE Journal of Solid-State Circuits, 2007 A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (VTHN ap 0.55 V and |VTHP| ap 0.75 V). The required on-chip capacitance is reduced to
Sai Kit Lau +2 more
openaire +3 more sources
Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input
IEEE Access, 2021 This paper presents the asynchronous digital low-dropout regulator (AD-LDO) with dual adjustment mode in ultra-low voltage input. The architecture of the proposed AD-LDO consists of the asynchronous control loop and the power PMOS array.
Wei-Bin Yang +3 more
doaj +1 more source
A 0.6 VIN 100 mV Dropout Capacitor-Less LDO with 220 nA IQ for Energy Harvesting System
Micromachines, 2023 A fully integrated and high-efficiency low-dropout regulator (LDO) with 100 mV dropout voltage and nA-level quiescent current for energy harvesting has been proposed and simulated in the 180 nm CMOS process in this paper.
Yuting Zhang, Qianhui Ge, Yanhan Zeng
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Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique
IEEE Access, 2021 This paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output ...
Muhammad Asif +6 more
doaj +1 more source
Supercapacitor assisted LDO (SCALDO) techniquean extra low frequency design approach to high efficiency DC-DC converters and how it compares with the classical switched capacitor converters [PDF]
, 2013 Supercapacitor assisted low dropout regulators (SCALDO) were proposed as an alternative design approach to DC-DC converters, where the supercapacitor circulation frequency (switching frequency) is in the order of few Hz to few 10s of Hz, with an output ...
Nihal Kulatana +5 more
core +1 more source
An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control
Energies, 2023 Digital low-dropout (DLDO) is widely used for power management in the system-on-chip (SoC) because of its low-voltage operation and process scalability.
Yen-Ming Chen, Ching-Jan Chen
doaj +1 more source
Supercapacitor assisted low dropout regulators (SCALDO) with reduced switches: A new approach to high efficiency VRM designs [PDF]
, 2013 Supercapacitor assisted low dropout (SCALDO) regulator is a new approach to develop high efficiency DC-DC converters with supercapacitors used for energy recovery.
Kularatna, Nihal +4 more
core +1 more source
IEEE Access, 2022 This paper presents the design of an output-capacitorless low-dropout voltage regulator (OCL-LDO) capable of driving a wide range of load capacitance and supplying a wide range of load current while maintaining excellent load and line regulations, thanks
Tanachai Limpisawas +1 more
doaj +1 more source
A fast transient low dropout regulator on 90 nm technology
Iteckne, 2015 En este trabajo se presenta el diseño de un regulador lineal de bajo diferencial de tensión para aplicaciones portátiles. El circuito propuesto consiste de un esquema simple de amplificación con una etapa de ganancia más el transistor de potencia. Además,
Héctor Iván Gómez-Ortiz +2 more
doaj +1 more source
Low‐ripple coarse‐fine digital low‐dropout regulator without ringing in the transient state
ETRI Journal, 2020 Herein, a low‐ripple coarse‐fine digital low‐dropout regulator (D‐LDO) without ringing in the transient state is proposed. Conventional D‐LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the ...
Ki‐Chan Woo, Byung‐Do Yang
doaj +1 more source