Results 241 to 250 of about 1,650,376 (292)

Low-voltage CMOS voltage squarer

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 2009
A voltage squarer based on bulk-driven PMOS transistors is proposed in this paper. Circuit topology employs a voltage attenuator and the quadratic I D /V G characteristic of a MOS in saturation. The squarer was designed with a 0.8V supply voltage using standard 0.35um CMOS process, which offers large value of threshold voltage.
George Raikos, Spyridon Vlassis
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Low voltage EELS—How low?

Ultramicroscopy, 2014
Using low beam energies in a (scanning) transmission electron microscope (S/TEM) has numerous advantages over higher beam energies. We discuss the performance of commonly available electron microscopes when being operated at reduced beam energies.
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Voltage control in low voltage systems with controlled low voltage transformer (CLVT)

CIRED 2012 Workshop: Integration of Renewables into the Distribution Grid, 2012
The rapidly growing penetration of Germany's distribution grids with all forms of DG causes a high pressure on voltage stability according to several normative guidelines. Beside conventional network reinforcements increasing short-circuit-power, new technical alternatives awake interest.
B. Werther, A. Becker, J. Schmiesing, E.-A. Wehrmann   +3 more
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A low-power low-voltage MOSFET-only voltage reference

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
A low-power low-voltage MOSFET-only voltage reference featuring very good temperature stability and referred to the positive power supply is proposed. It compensates for the temperature dependence of a gate-to-source voltage of an MOS transistor working in the weak inversion region with a proportional-to-absolute-temperature voltage generated by a pair
F. Bedeschi, E. Bonizzoni, A. Fantini, C. Resta, G. Torelli   +4 more
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Low Power, Low Voltage, Low Drop-Out On-chip Voltage Regulator

2020
Extremely low power, low voltage complete on-chip low drop-out voltage regulator (LDO) is presented. The LDO receives an unregulated supply of 0.5–1 V and regulates it to 0.4 V nominal output utilizing a 0.1 V on-chip reference voltage. A load capacitor of just 1pf is assumed to be present at LDO output. Designed voltage reference and complete LDO were
Gopal Agarwal, Ved Vyas Dwivedi
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A low voltage CMOS low drop-out voltage regulator

SPIE Proceedings, 2009
A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes
Salma Ali Bakr, Tanvir Ahmad Abbasi, Mohammas Suhaib Abbasi, Mohamed Samir Aldessouky, Mohammad Usaid Abbasi   +4 more
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A low-voltage low-power voltage reference based on subthreshold MOSFETs

IEEE Journal of Solid-State Circuits, 2003
In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV ...
GIUSTOLISI, Gianluca, PALUMBO, Gaetano, Criscione M, Cutri F.   +3 more
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High Voltage Versus Low Voltage

Physical Therapy, 1986
To the Editor: The conclusions stated in the article “High Voltage Versus Low Voltage Electrical Stimulation: Force of Induced Muscle Contraction and Perceived Discomfort in Healthy Subjects” (Physical Therapy 66:1209–1214, 1986) contradict an extensive body of literature1–5 that suggests that optimal pulse duration for neuromuscular stimulation in ...
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Low-Voltage Low-Power Amplifiers

1995
Low-voltage and low-power amplifiers are strongly limited in dynamic range (DR) and bandwidth (B). The maximum dynamic-range/supply-power ratio is restricted to DR/sub max//P/sub sup/ = /spl pi//16 kTBe by thermal noise in resistors. To obtain this maximum value, several rail-to-rail (R-R) input stages and R-R output stages biased in class-AB are ...
Ron Hogervorst, Johan H. Huijsing, Klaas-Jan de Langen, Ruud G. H. Eschauzier   +3 more
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Low-Voltage DML

2020
This chapter examines DML performance, energy consumption, static noise margins, delay distribution, robustness, and other design metrics under low-voltage operation. It still focuses on the gate level and DML operations in subthreshold and near-threshold regions illustrated using the transregional model.
Itamar Levi, Alexander Fish
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