Results 241 to 250 of about 11,136,150 (300)

Voltage control in low voltage systems with controlled low voltage transformer (CLVT)

CIRED 2012 Workshop: Integration of Renewables into the Distribution Grid, 2012
The rapidly growing penetration of Germany's distribution grids with all forms of DG causes a high pressure on voltage stability according to several normative guidelines. Beside conventional network reinforcements increasing short-circuit-power, new technical alternatives awake interest.
B. Werther, A. Becker, J. Schmiesing, E.-A. Wehrmann   +3 more
openaire   +1 more source

Multithreshold voltage low-swing/low-voltage techniques in logic gates

Integration, 2004
A low-power design circuit using low-swing voltage technique is proposed in this paper. The proposed technique could be used in order to decrease the power dissipation in three different types of logic gates namely the complementary pass-transistor logic (CPL), the cascade voltage switch logic (CVSL), and the domino logic. The main idea of the proposed
Abdoul Rjoub, Odysseas G. Koufopavlou
openaire   +2 more sources

A low-voltage low-power capacitive-feedback voltage controlled oscillator

Integration, 2018
This paper introduces an LC voltage controlled oscillator (VCO) in current-reuse configuration where transistors are biased in subthreshold region to save power consumption. A capacitive-feedback technique is employed to increase the output swing above the supply voltage and potential ground.
Habib Rastegar, Saeid Zare, Jee-Youl Ryu
openaire   +1 more source

A Low-Voltage Electrocardiogram

JAMA Internal Medicine
This case report describes a woman in her 60s who had an inferior wall myocardial infarction 1 year prior and presented to the emergency department with worsening dyspnea and anasarca for the past 2 months.
Asharam, Panda, S S, Mishra
openaire   +2 more sources

Low-Power Wordline Voltage Generator for Low-Voltage Flash Memory

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006
Wordline voltage generating circuit with high speed active mode and low power standby mode is proposed. In the active mode, two different ring oscillators with high clock frequency (fCLK) 170 MHz, and low clock frequency (fCLK) 25 MHz which is also the operating frequency of the entire circuit, are employed.
Tzu-Ming Wang, Ming-Dou Ker, Steve Yeh, Ya-Chun Chang   +3 more
openaire   +2 more sources

A low supply-dependence fully-MOSFET voltage reference for low-voltage and low-power

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008
A low supply-dependence fully-MOSFET voltage reference for low-voltage and low-power is presented. It compensates for the temperature dependence of a current based on gate-source voltage of a MOSFET operating in subthreshold region with a low supply-dependence PTAT current, and exhibits very low supply-dependence for supply voltage.
Jun Shu, Min Cai
openaire   +2 more sources

Low-voltage linear voltage regulator suitable for memories

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
In this communication a low-voltage linear voltage regulator in CMOS technology is presented. It is based on a two class-AB gain stage and, hence, does not suffer from internal slew-rate limitation when very large load capacitances are used. The linear regulator suitable for memory application was designed in a 0.35 /spl mu/m standard CMOS technology ...
W. ALOISI, S. M. BILLE, PALUMBO, Gaetano
openaire   +2 more sources

Low voltage EELS—How low?

Ultramicroscopy, 2014
Using low beam energies in a (scanning) transmission electron microscope (S/TEM) has numerous advantages over higher beam energies. We discuss the performance of commonly available electron microscopes when being operated at reduced beam energies.
openaire   +2 more sources

Low Power, Low Voltage, Low Drop-Out On-chip Voltage Regulator

2020
Extremely low power, low voltage complete on-chip low drop-out voltage regulator (LDO) is presented. The LDO receives an unregulated supply of 0.5–1 V and regulates it to 0.4 V nominal output utilizing a 0.1 V on-chip reference voltage. A load capacitor of just 1pf is assumed to be present at LDO output. Designed voltage reference and complete LDO were
Gopal Agarwal, Ved Vyas Dwivedi
openaire   +1 more source

Low-voltage ULSI design

IEEE Journal of Solid-State Circuits, 1993
An overall view on low-voltage device and circuit design is presented, beginning with a discussion of the low-voltage limit. Low-voltage device design is then described. Low-voltage CMOS and BiCMOS logic circuits are discussed. Circuit techniques for the low-voltage DRAMs and SRAMs are presented.
Katsuhiro Shimohigashi, Koichi Seki
openaire   +2 more sources