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A High-Performance, Conflict-Free Memory-Access Architecture for Modular Polynomial Multiplication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zeming Cheng   +2 more
exaly  

Meta: A Memory-Efficient Tri-Stage Polynomial Multiplication Accelerator Using 2D Coupled-BFUs

IEEE Transactions on Circuits and Systems I: Regular Papers
Lin Ding, Zhaojun Lu
exaly  

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