Results 291 to 300 of about 2,555,131 (350)

Screening methods and experience with MOS memory

Microelectronics Reliability, 1978
Abstract This paper describes the experience of Bell-Northern Research and Northern Telecom Ltd. with MOS dynamic RAMS in high reliability switching systems. Various failure mechanisms of the MOS memory devices and the screening procedures, implemented in Northern Telecom Ltd. to weed out weak devices, are explained.
R.V. Pappu, E. Harris, M. Yates
openaire   +2 more sources

A new measurement method of MOS transistor parameters

Solid-State Electronics, 1990
Abstract A new method for the extraction of some of the main physical parameters characterizing an MOS process is presented. This method requires current measurements for small drain voltages to be performed at least on two transistors which differ only for the channel length. In particular it makes it possible to determine the threshold voltage, the
CIOFI, Carmine, MACUCCI M., PELLEGRINI B.   +2 more
openaire   +3 more sources

Time efficient method for MOS circuit extraction

1993 IEEE International Symposium on Circuits and Systems, 2002
A new method for circuit extraction from VLSI masks for any MOS technology is presented. The algorithms operate on mask edges allowing rapid connectivity and device extraction. A new approach to non rectilinear polygon overlap analysis is presented. The scanline algorithm used is modified to meet geometric features imposed by technology. The transistor
Doerffer, Karol, Anton, Oskar, Mlynski, Dieter A.   +2 more
openaire   +1 more source

A Method of MOS Evaluation for Video Based Services

2016 10th International Conference on the Quality of Information and Communications Technology (QUATIC), 2016
This paper deals with a method for QoE evaluationfor the services transmitting large amount of data perceived by the end user in relatively short time periods, e.g. streaming video in mobile operator network. Surprising factor of the new method relies on QoE/MOS evaluation, which is based on the smallest building unit which is a frame for a video ...
Martin Kollar, Arkadiusz Zieba
openaire   +2 more sources

Methods to improve digital MOS macromodel accuracy

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
This paper presents accurate series-transistor reduction techniques which extend the applicability of linear and nonlinear macromodels to more complex structures through accurately modeling the channel length modulation effect, effective transconductance, input terminal position dependence, parasitic capacitances, such as gate coupling capacitances ...
Jeong-Taek Kong, David Overhauser
openaire   +1 more source

Comparison of semiempirical MO methods for open‐shell systems

Journal of Computational Chemistry, 1988
AbstractThe use of AM1, MNDO, and MNDOC semiempirical MO methods for calculation of heats of formation and ionization potentials of a series of 38 radicals are described. AM1 and MNDO calculations are reported using both half‐electron (HE) and Unrestricted Hartree Fock (UHF) wavefunctions.
Higgins, D., Thomson, C., Thiel, W.
openaire   +2 more sources

Fast Methods for Switch-Level Verification of MOS Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist.
Douglas S. Reeves, Mary Jane Irwin
openaire   +1 more source

A Dense Gate Matrix Layout Method for MOS VLSI

IEEE Journal of Solid-State Circuits, 1980
A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of intersecting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout ...
A.D. Lopez, H.-F.S. Law
openaire   +1 more source

New simulation methods for MOS VLSI timing and reliability

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers, 2002
A novel approach to incorporating the channel length modulation in a direct-equation solving fast timing simulator is presented along with a mixed event-driven and waveform relaxation algorithm to handle MOS VLSI circuits with feedback. Simulation speedup of 3N over SPICE-like simulators has been observed, where N is the number of transistors.
Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang   +2 more
openaire   +1 more source