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Predicting multi-core performance
Proceedings of the 3rd International Workshop on Multicore Software Engineering, 2010Multi-core technology is an emerging hardware trend that provides significant capabilities for computationally expensive applications. However, it also demands a paradigm shift in the software industry, Software developers need to think about the best distribution of software components across the available CPUs, and trade-off the computational ...
Akbar Siami Namin +2 more
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Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies, 2009
This research presents a hierarchical formal model capable of providing adjustable levels of service and quality of assurance, which is especially suitable for multi-core processor systems. The multi-layered architecture supports multiple levels of fault detection, masking, and dynamic load balancing.
Axel Krings +3 more
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This research presents a hierarchical formal model capable of providing adjustable levels of service and quality of assurance, which is especially suitable for multi-core processor systems. The multi-layered architecture supports multiple levels of fault detection, masking, and dynamic load balancing.
Axel Krings +3 more
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Multi-core design automation challenges
Proceedings of the 44th annual conference on Design automation - DAC '07, 2007The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking of early analysis tools around shared data and an ...
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Chinese Physics Letters, 2020
We propose multi-core conformal lenses by combining conformal transformation optics with absolute instruments. Depending on the cores and incident angles, the conformal lenses have tunable functionalities like focusing, reflection, and transparency, thereby providing a feasible general method for designing multi-functional devices.
Xinghong Zhu +2 more
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We propose multi-core conformal lenses by combining conformal transformation optics with absolute instruments. Depending on the cores and incident angles, the conformal lenses have tunable functionalities like focusing, reflection, and transparency, thereby providing a feasible general method for designing multi-functional devices.
Xinghong Zhu +2 more
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Heterogeneous multi-core systems
Proceedings of the 2012 workshop on Domain-specific modeling, 2012This paper examines tradeoffs in extending a UML profile, or developing a new DSML for a particular domain. Questions are presented which help to make an objective decision. A case study is presented to address system design in heterogeneous multi-core systems.
David McKean, Jonathan Sprinkle
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2015
In this chapter, DICE2D is parallelized for multi-core PCs. First, a brief introduction of parallel computing using multi-core PCs and its implementation using the Parallel Computing Toolbox® of MATLAB® is presented. Then, the performance of serial DICE2D is analyzed to aid the selection of essential sections that might be effective for parallelization.
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In this chapter, DICE2D is parallelized for multi-core PCs. First, a brief introduction of parallel computing using multi-core PCs and its implementation using the Parallel Computing Toolbox® of MATLAB® is presented. Then, the performance of serial DICE2D is analyzed to aid the selection of essential sections that might be effective for parallelization.
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Frontiers in Optics 2015, 2015
The operation of multi-core fiber lasers with and without supermode selection will be discussed. Supermode specific gain measurements and roundtrip losses, as well as the dynamic behavior of multi-core fiber lasers will be presented.
J. Anderson +5 more
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The operation of multi-core fiber lasers with and without supermode selection will be discussed. Supermode specific gain measurements and roundtrip losses, as well as the dynamic behavior of multi-core fiber lasers will be presented.
J. Anderson +5 more
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2012
A method of operating a multi-core processor, where each processor core is provided with its own private cache and the device comprises or has access to a common memory. The method comprises executing a processing thread on a selected first processor core, and implementing a normal access mode for executing an operation within a processing thread and ...
ERICSSON TELEFON AB L M +2 more
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A method of operating a multi-core processor, where each processor core is provided with its own private cache and the device comprises or has access to a common memory. The method comprises executing a processing thread on a selected first processor core, and implementing a normal access mode for executing an operation within a processing thread and ...
ERICSSON TELEFON AB L M +2 more
openaire +1 more source
2013
Multiple processors, microcontrollers, or DSPs have been used in embedded systems to distribute control and data flow according to the application at hand. The recent trends of incorporating multiple cores in the same chip significantly expands the processing power of such heterogeneous systems.
Ricardo Chessini Bose +5 more
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Multiple processors, microcontrollers, or DSPs have been used in embedded systems to distribute control and data flow according to the application at hand. The recent trends of incorporating multiple cores in the same chip significantly expands the processing power of such heterogeneous systems.
Ricardo Chessini Bose +5 more
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2014
We finally are able to specify a multi-core MIPS machine, build it, and show that it works. Clearly the plan is to take pipelined MIPS machines from Chap. 7 and connect them to the shared memory system from Chap. 8. Before we can do this, however, we have to address a small technical problem: the pipelined machine was obtained by a transformation from ...
Mikhail Kovalev +2 more
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We finally are able to specify a multi-core MIPS machine, build it, and show that it works. Clearly the plan is to take pipelined MIPS machines from Chap. 7 and connect them to the shared memory system from Chap. 8. Before we can do this, however, we have to address a small technical problem: the pipelined machine was obtained by a transformation from ...
Mikhail Kovalev +2 more
openaire +1 more source