Results 261 to 270 of about 41,062 (305)
Research on the Embedded Heterogeneous Multi-core Design Method for 100GbE Network Processor
Procedia Engineering, 2012 We proposed a design method of heterogeneous multi-core processor on chip. In our design flow, we structured a computing model mapped onto the processor's micro architecture, and structured a work-load model mapped onto the system architecture.
Bian, Dong +2 more
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2020
This section contains a moderately renovated proof of the main result of [KMP14] establishing the correctness of a multi core processor with pipelined processor cores.
Petro Lutsyk +2 more
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This section contains a moderately renovated proof of the main result of [KMP14] establishing the correctness of a multi core processor with pipelined processor cores.
Petro Lutsyk +2 more
openaire +1 more source
2014
We finally are able to specify a multi-core MIPS machine, build it, and show that it works. Clearly the plan is to take pipelined MIPS machines from Chap. 7 and connect them to the shared memory system from Chap. 8. Before we can do this, however, we have to address a small technical problem: the pipelined machine was obtained by a transformation from ...
Mikhail Kovalev +2 more
openaire +1 more source
We finally are able to specify a multi-core MIPS machine, build it, and show that it works. Clearly the plan is to take pipelined MIPS machines from Chap. 7 and connect them to the shared memory system from Chap. 8. Before we can do this, however, we have to address a small technical problem: the pipelined machine was obtained by a transformation from ...
Mikhail Kovalev +2 more
openaire +1 more source
Storage Architecture for an On-chip Multi-core Processor
2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009Modern multi-core processor architectures strive for the highest possible performance of various applications. This paper discusses a triple-based multi-core architecture which supports object-oriented methodology and applications in hardware level.
Mengxiao Liu +3 more
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Memory System Design for a Multi-core Processor
2008 International Conference on Complex, Intelligent and Software Intensive Systems, 2008Multi-core processor has become hot research area recently. Cache results in high cost to maintain consistency between different data copies in multi-core processor especially in many-core processor. A hybrid memory architecture is proposed for the specific multi-core processor which uses cache for instruction while local storage for data.
Jianjun Guo +6 more
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A Task Scheduling Algorithm for Multi-core Processors
2013 International Conference on Parallel and Distributed Computing, Applications and Technologies, 2013With the widespread use of multi-core processors, task scheduling for multi-core processors has become a hot issue. Many researches have been done on task scheduling from various perspectives. However, the existing task scheduling algorithms still have some drawbacks, such as low processor utilization rate, high complexity, and so on.
Xuanxia Yao, Peng Geng, Xiaojiang Du
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POWER7 multi-core processor design
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, 2009POWER series of processors are the building block for IBM's p-Series servers. With its leading edge microarchitecture, technology and efficient implementation, POWER processors are the dominating RISC processor technology today. POWER processors form the building block for IBM's p-Series servers, which have the largest UNIX marketshare.
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Communication Control for Multi-core Processors
2012 Third International Conference on Digital Manufacturing & Automation, 2012A reconfigurable System-on-Chip (SoC) for multimedia application was introduced in this paper, where the SoC consisted of a master processor and slave processor. We individually simulated the master processor with DLX pipeline processor and the slave processor with Xtensa processor that was able to establish a excellent multimedia processor with multi ...
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Defensive loop tiling for multi-core processor
Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, 2012Loop tiling is a compiler transformation that tailors an application's working set to fit in a cache hierarchy. On today's multicore processors, part of the hierarchy, especially the last level cache (LLC) is shared. In this paper, we show that cache sharing requires special types of tiling depending on the co-run programs.
Bin Bao, Xiaoya Xiang
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A Reconfigurable Audio Beamforming Multi-Core Processor
2011Over the last years, the Beamforming technique has been adopted by the audio engineering society to amplify the signal of an acoustic source, while attenuating any ambient noise. Existing software implementations provide a flexible customizing environment, however they introduce performance limitations and excessive power consumption overheads.
Dimitris Theodoropoulos 0001 +2 more
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