Results 21 to 30 of about 1,489,032 (375)
Predictive Power Management for Multi-core Processors [PDF]
, 2011 Predictive power management provides reduced power consumption and increased performance compared to reactive schemes. It effectively reduces the lag between workload phase changes and changes in power adaptations since adaptations can be applied immediately before a program phase change.
Lloyd Bircher, William, John, Lizy
openaire +2 more sources
Core Interface Optimization for Multi-core Neuromorphic Processors
2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2023 Hardware implementations of Spiking Neural Networks (SNNs) represent a promising approach to edge-computing for applications that require low-power and low-latency, and which cannot resort to external cloud-based computing services. However, most solutions proposed so far either support only relatively small networks, or take up significant hardware ...
Su, Zhe +3 more
openaire +2 more sources
Parallel Integer Polynomial Multiplication [PDF]
, 2016 We propose a new algorithm for multiplying dense polynomials with integer coefficients in a parallel fashion, targeting multi-core processor architectures.
Chen, Changbo +5 more
core +4 more sources
Garbage collection auto-tuning for Java MapReduce on Multi-Cores [PDF]
, 2011 MapReduce has been widely accepted as a simple programming pattern that can form the basis for efficient, large-scale, distributed data processing. The success of the MapReduce pattern has led to a variety of implementations for different computational ...
Allen E. +10 more
core +1 more source
Hardware synchronization for embedded multi-core processors [PDF]
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011 Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establishing coherence and consistency for different types of ...
Christian Stoif +3 more
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Using graphics processors to accelerate the computation of the matrix inverse [PDF]
, 2011 We study the use of massively parallel architectures for computing a matrix inverse. Two different algorithms are reviewed, the traditional approach based on Gaussian elimination and the Gauss-Jordan elimination alternative, and several high ...
Ezzatti, Pablo +2 more
core +1 more source
The potential of programmable logic in the middle: cache bleaching [PDF]
, 2020 Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns.
Mancuso, Renato, Roozkhosh, Shahin
core +1 more source
Flow Assignment in Multi-Core Network Processors [PDF]
, 2019 In modern telecommunication networks, the trend toward “softwarization” is shifting the execution of switching and protocol functionalities from specialized devices to general purpose hardware located in datacenters or at the network edge. Incoming flows generated by User Equipment are processed by different functional modules executed in Virtual ...
F. Davoli, M. Marchese, F. Patrone
openaire +1 more source
The parallel processing design of particle swarm optimization based on TMS320C6678
Dianzi Jishu Yingyong, 2018 In view of the real-time requirement of PSO in practical applications, the parallelism of the algorithm is analyzed. According to the architecture characteristics of TMS320C6678 multi-core processor, this paper designs a local parallel and global serial ...
Zhang Qingxiang, Guo Xutao, Wang Jing
doaj +1 more source
parMERASA Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability [PDF]
, 2013 International audienceEngineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time
Abella, Jaume +27 more
core +2 more sources