Results 21 to 30 of about 41,062 (305)
Rationale for a 3D heterogeneous multi-core processor [PDF]
2013 IEEE 31st International Conference on Computer Design (ICCD), 2013 Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most efficient ...
Eric Rotenberg +9 more
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Improved Scheduling Algorithm for Synchronous Data Flow Graphs on a Homogeneous Multi-Core Systems
Algorithms, 2022 In order to accelerate the execution of streaming applications on multi-core systems, this article studies the scheduling problem of synchronous data flow graphs (SDFG) on homogeneous multi-core systems.
Lei Wang, Chenguang Wang, Huabing Wang
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Dianzi Jishu Yingyong, 2018 A design of multi-view on-line monitoring system for longitudinal rip of conveyor belt is presented, which can be used to detect longitudinal rip of conveyor belt.
Wan Quanting +3 more
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IEEE Access, 2019 While single-ISA heterogeneous multi-core processors are widely used in mobile computing, typical code generations optimize the code for a single target core, leaving it less suitable for the other cores in the processor.
Junmo Park +3 more
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Advances in Electrical and Computer Engineering, 2014 In analysis of minutiae based fingerprint systems, fingerprints needs to be pre-processed. The pre-processing is carried out to enhance the quality of the fingerprint and to obtain more accurate minutiae points.
GORGUNOGLU, S. +3 more
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High-performance Architecture of Network Intrusion Prevention Systems
EAI Endorsed Transactions on Scalable Information Systems, 2014 Software-based Network Intrusion Prevention Systems have difficulty in handling high speed links. Network processor (NP) is an emerging field of programmable processors that are optimized to implement network data.
Zhao Yueai +3 more
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Core Interface Optimization for Multi-core Neuromorphic Processors
2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2023 Hardware implementations of Spiking Neural Networks (SNNs) represent a promising approach to edge-computing for applications that require low-power and low-latency, and which cannot resort to external cloud-based computing services. However, most solutions proposed so far either support only relatively small networks, or take up significant hardware ...
Zhe Su +3 more
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Energy Efficiency Optimization Scheme for Multi-core Processor Under Power Consumption Constraint [PDF]
Jisuanji gongcheng, 2017 Keeping processor power consumption under budget can reduce the cost of cooling and improve the system reliability.Most existing energy efficiency optimization schemes are profile-based offline schemes,which may reduce practicality.Furthermore ...
QIU Xiaojie,AN Hong,CHEN Junshi,CHI Mengxian,JIN Xu
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FEBS Letters, EarlyView.We identified a systemic, progressive loss of protein S‐glutathionylation—detected by nonreducing western blotting—alongside dysregulation of glutathione‐cycle enzymes in both neuronal and peripheral tissues of Taiwanese SMA mice. These alterations were partially rescued by SMN antisense oligonucleotide therapy, revealing persistent redox imbalance as ...
Sofia Vrettou, Brunhilde Wirth
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Advances in Electrical and Computer Engineering, 2019 This paper presents the authors' research in the field of specialized optimizing assembly language compilers for embedded real-time soft-core processor systems on FPGAs.
KIRCHHOFF, M., WAGNER, L., FENGLER, W.
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