Results 251 to 260 of about 22,844 (300)

SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction. [PDF]

Micromachines (Basel)
Li T, Tian J, Qi J.
europepmc   +1 more source

Performance evaluation of GPU-based parallel sorting algorithms. [PDF]

PLoS One
Ala'anzy MA, Tolendi N, Baubek B, Algarni A.   +3 more
europepmc   +1 more source

Run-time power estimation for mobile and embedded asymmetric multi-core CPUs

Merrett, Geoff V., Hashimi, B.M., Das, Anup K., Walker, Matthew J.   +3 more
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Parallelization of AdaBoost algorithm on multi-core processors

2008 IEEE Workshop on Signal Processing Systems, 2008
This paper examines and extracts the parallelism in the AdaBoost person detection algorithm on multi-core processors. As multi-core processors become pervasive, effectively executing many threads simultaneously is crucial in harnessing the computation power.
Yen-Kuang Chen
exaly   +2 more sources

On the effective parallel programming of multi-core processors.

, 2010
Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are difficult to program.
Varbanescu, A.L. (author), Varbanescu, A.L.   +1 more
openaire   +2 more sources

Nearly symmetric multi-core processors

Proceedings of the 11th ACM SIGOPS Asia-Pacific Workshop on Systems, 2020
Multi-core processors are commonplace and continue to require rethinking (not only) in system software development. It is still difficult to operate several functionally identical computing cores efficiently. One misconception is to assume that functionally identical cores of a multi-core processor will behave non-functionally alike, especially at the ...
Stefan Reif, Benedict Herzog, Fabian Hügel, Timo Hönig, Wolfgang Schröder-Preikschat   +4 more
openaire   +1 more source

Physical-aware predictive dynamic thermal management of multi-core processors

Journal of Parallel and Distributed Computing, 2016
The advances in silicon process technology have made it possible to have processors with larger number of cores. The increment of cores number has been hindered by increasing power consumption and heat dissipation due to high power expenditure in a small
Bagher Salami, Hamid Noori, Farhad Mehdipour   +2 more
exaly   +2 more sources

A freespace crossbar for multi-core processors

Proceedings of the 22nd annual international conference on Supercomputing, 2008
A new package-level interconnect is described that adapts carbon nanoemissive display technology to create an inexpensive package-level freespace crossbar with single-cycle source-to-target latency. Interconnections are made using filamentary electron beams as the data transmission medium.
Michel N. Victor, Aris K. Silzars, Edward S. Davidson   +2 more
openaire   +1 more source

Multi Core Processors

2020
This section contains a moderately renovated proof of the main result of [KMP14] establishing the correctness of a multi core processor with pipelined processor cores.
Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul   +2 more
openaire   +1 more source