Results 171 to 180 of about 1,018 (190)
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An FPGA-based Dead-time Computation Technique for Neutral Point Clamped Multilevel Inverter (NPC-MLI)

2020 IEEE 17th India Council International Conference (INDICON), 2020
In order to prevent the occurrence of the short circuit between the identical phase-leg semiconductor switches, dead-time is injected in the pulse width modulation (PWM) voltage source multilevel inverters (MLIs). This paper proposes a mathematically formulated dead-time computation technique for neutral-point clamped multilevel inverters (NPC-MLIs ...
Rishiraj Sarker, Asim Datta
openaire   +1 more source

REDUKSI HARMONISA MENGGUNAKAN CASCADED H-BRIDGE MULTILEVEL INVERTER (MLI) SATU FASA DENGAN TEKNIK MULTICARRIER SPWM

MUSTEK ANIM HA, 2022
Gangguan harmonik keluaran tegangan listrik pada inverter dapat menyebabkan peralatan yang terhubung mengalami kerusakan. Inverter konvensional dengan topologi full bridge menggunakan filter pasif untuk mengatasi gangguan harmonik. Namun, membutuhkan nilai komponen yang cukup besar sehingga menambah biaya dan ruang pada inverter.
Paulus Mangera   +3 more
openaire   +1 more source

Switched capacitor based single DC source boost multilevel inverter (S 2 -MLI) featuring isolation based soft charging with minimum device count

International Journal of Emerging Electric Power Systems, 2021
Abstract Multilevel inverters (MLIs) have formed a new wave of interest in research and industry. Switched capacitor-based multilevel inverters are used to avoid the need for multiple separated DC sources compared to cascaded MLIs.
Tamiru Debela, Jiwanjot Singh
openaire   +1 more source

FPGA Implementation of Phase Disposition PWM (PD-PWM) Strategy for Cascaded H-Bridge Multilevel Inverter (CHB-MLI)

2020 IEEE Applied Signal Processing Conference (ASPCON), 2020
Field-programmable gate array (FPGA)-based multi-carrier pulse-width modulation (MCPWM) generation technique is desirable for high-frequency dc/ac converter application where a fast-switching response is the primary concern. This paper offers an FPGA-based high-frequency, multi-carrier phase disposition pulse-width modulation (PDPWM) generation ...
Rishiraj Sarker   +2 more
openaire   +1 more source

A level-doubling network (LDN) for cross-connected sources based multilevel inverter (CCS-MLI)

2014 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), 2014
As multilevel inverters are gaining importance, new topologies are being proposed especially for increased number of levels while reducing the number of power switches. In this paper, a level-doubling network (LDN) is proposed for the recently proposed ‘cross-connected sources based multilevel inverter (CCS-MLI)’ topology.
Niraj Kumar Dewangan   +3 more
openaire   +1 more source

A Fault-Tolerant Multilevel Inverter (FT-MLI) Topology for Electric Vehicle Applications

2023 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific), 2023
Marif Daula Siddique   +3 more
openaire   +1 more source

Modeling of nine level switched-capacitor based Multilevel Inverter (MLI) topology

AIP Conference Proceedings, 2023
Purnesh Patel   +2 more
openaire   +1 more source

Reduction of Total Harmonic Distortion in H-bridge Hybrid Multilevel Inverter (MLI) Using POD Technique with Linear Quadratic Regulator for Solar Inverters

2022 International Conference on Innovative Computing, Intelligent Communication and Smart Electrical Systems (ICSES), 2022
P. Loganathan, A. Kathar Hussain
openaire   +1 more source

High‐gain nine‐level switched‐capacitor multilevel inverter featuring less number of devices and leakage current

International Journal of Circuit Theory and Applications, 2023
Tamiru Debela, Jiwanjot Singh
exaly  

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