Results 101 to 110 of about 109,785 (250)

RasoulFaraji/Hybrid-Binary-Unary-Multiplier v.0

, 2019
Low-Cost Constant Coefficient Hybrid Binary-Unary Multiplier for DSP ...
RasooulFaraji
core   +1 more source

Strong Lead‐Free Bioinspired Piezoceramics for Durable Energy Transducers

Advanced Functional Materials, EarlyView.
We fabricated brick‐and‐mortar lead‐free piezoceramics with Bi0.5Na0.5TiO3 monocrystal platelets as bricks and amorphous silica as mortar. The alignment of the bricks and the presence of the amorphous silica led to anisotropic residual stresses. These residual stresses increase the samples toughness, strength and durability while the brick alignment ...
Ruxue Yang, Temesgen Tadeyos Zate, Peiren Wang, Soumyajit Mojumder, Elo Overgaard Mogensen, Oriol Gavalda‐Diaz, Zihe Li, Shitong Zhou, Ajeet Kumar, James Roscow, Hamideh Khanbareh, Astri Bjørnetun Haugen, Florian Bouville   +12 more
wiley   +1 more source

Universal-Gate-Driven Efficient 3-D Vedic Multiplier Designs for Nanoscale Logic Systems With Application of High-Performance Computing

IEEE Access
Perpendicular Nanomagnetic Logic (pNML) offers a promising post-CMOS paradigm that combines nonvolatility, near-zero static power consumption, and high radiation tolerance.
Naga Raju Bathula, Neeraj Kumar Misra
doaj   +1 more source

Noise‐Limited Bit Precision in Ferroelectric Synaptic Transistors for High‐Resolution Neuromorphic Computing

Advanced Functional Materials, EarlyView.
Low‐frequency noise spectroscopy defines the resolvable conductance states of synaptic FeFETs by coupling read‐current fluctuation with usable dynamic range. The resulting noise‐limited bit precision establishes a universal, device‐agnostic reliability metric beyond the memory window, enabling quantitative benchmarking and rational design of high ...
Jaehong Park, Yeonseop Shin, Changhyeon Han, Sangwoo Kim, Eunchan Park, Youngchan Cho, Jaehong Min, Hyunjun Ahn, Jaekyoung Park, Cheol‐Woong Yang, Jangsaeng Kim, Daewoong Kwon, Wonjun Shin   +12 more
wiley   +1 more source

n-Jordan multipliers [PDF]

Surveys in Mathematics and its Applications, 2018
Let A be a Banach algebra, X be a Banach left A-module and n ≥ 2 be an integer. A bounded linear operator T: A → X is called an n-Jordan multiplier if for each a ∈ A, T(an)=a· T(an-1).
Mohammad Fozouni
doaj  

A Multiplier Based on the Algorithm of Chinese Abacus

, 2012
[[abstract]]A 4x4 and 8x8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4x4 and 8x8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5%
Lin, Chien-Hung; Yi, Shu-Chung; Chen, Jin-Jia
core  

Memristive‐Gated RC‐Delay Synaptic Transistors for Time‐Encoded Analog in‐Memory Computing

Advanced Functional Materials, EarlyView.
A Memristive‐Gated Transistor for Time‐Encoded Analog In‐Memory Computing — By exploiting the RC delay of a self‐rectifying interface‐type memristor, nonlinear I–V distortion is structurally bypassed, enabling 3‐bit nonvolatile memory, spike‐timing‐based analog encoding, and hardware‐calibrated reservoir‐computing validation within a unified device ...
Yun‐Seo Shin, Eunjoo Yoo, Ki‐Hoon Son, Hyun‐Sik Kim, Dae‐Hee Han, Jeong Hyeon Son, Seung Hwan Lee, Hong‐Sub Lee   +7 more
wiley   +1 more source

"Hypothetical Integration in a Social Accounting Matrix and Fixed-price Multiplier Analysis" [PDF]

This study proposes a simple modification to a Social Accounting Matrix (SAM) in order to analyze the multiplier effects of a new sector. A different input composition, or technology, of the sector makes a conventional analysis of final-demand injections
Kijong Kim
core  

Emerging Post‐CMOS Hardware Neurons for Brain‐Inspired Computing: Devices, Circuits, and System Integration

Advanced Functional Materials, EarlyView.
The physical realization of artificial neurons is a critical challenge for energy‐efficient neuromorphic computing. This review presents a comprehensive analysis of the evolution of artificial neuron implementations from conventional CMOS to emerging post‐CMOS technologies.
Kannan Udaya Mohanan, Hocheon Yoo, Benoît H. Lessard, Ioannis Kymissis, Chang‐Hyun Kim   +4 more
wiley   +1 more source

A multiplier design based on additive tree compression and multiplier encoding optimization

Dianzi Jishu Yingyong
The fixed-point multiplier is one of the commonly used computing units in modern signal processing, and its overall performance directly determines the competitiveness of the system.
Wang Shouhua, Wang Mingxu, Sun Xiyan
doaj   +1 more source