Results 31 to 40 of about 78,420 (46)

Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing

IACR Cryptology ePrint Archive, 2018
Blocking microarchitectural (digital) side channels is one of the most pressing challenges in hardware security today. Recently, there has been a surge of effort that attempts to block these leakages by writing programs data obliviously.
Jiyong Yu, Lucas Hsiung, Mohamad El Hajj, Christopher W. Fletcher   +3 more
semanticscholar   +1 more source

Prenatal Mancozeb Exposure, Excess Manganese, and Neurodevelopment at 1 Year of Age in the Infants’ Environmental Health (ISA) Study

Environmental Health Perspectives, 2018
Background: Although growing evidence suggests that early-life excess manganese (Mn) impairs neurodevelopment, data on the neurodevelopmental effects of mancozeb, a fungicide containing Mn, and its main metabolite ethylenethiourea (ETU) are limited ...
A. Mora, L. Córdoba, J. C. Cano, D. Hernández-Bonilla, Larissa A. Pardo, L. Schnaas, Donald R. Smith, J. Menezes-Filho, D. Mergler, C. Lindh, B. Eskenazi, B. van Wendel de Joode   +11 more
semanticscholar   +1 more source

Modelling the ARMv8 architecture, operationally: concurrency and ISA

ACM-SIGACT Symposium on Principles of Programming Languages, 2016
In this paper we develop semantics for key aspects of the ARMv8 multiprocessor architecture: the concurrency model and much of the 64-bit application-level instruction set (ISA).
Shaked Flur, Kathryn E. Gray, Christopher Pulte, Susmit Sarkar, A. Sezgin, Luc Maranget, Will Deacon, Peter Sewell   +7 more
semanticscholar   +1 more source

SparseCore: stream ISA and processor specialization for sparse computation

International Conference on Architectural Support for Programming Languages and Operating Systems, 2022
G. Rao, Jingji Chen, Jason Yik, Xuehai Qian   +3 more
semanticscholar   +1 more source

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RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography

IEEE transactions on computers, 2023
Due to the recent advances in new communication standards, such as 5G New Radio and beyond 5G, and in quantum computing and communications, new requirements for integrating processors into nodes have appeared.
Yao-Ming Kuo, F. García-Herrero, Ó. Ruano, J. A. Maestro   +3 more
semanticscholar   +1 more source

Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics

Micro, 2021
The importance of open-source hardware and software has been increasing. However, despite GPUs being one of the more popular accelerators across various applications, there is very little open-source GPU infrastructure in the public domain. We argue that
Blaise Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, Hyesoon Kim   +3 more
semanticscholar   +1 more source

SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors

Design Automation Conference, 2022
Custom instructions extending a base ISA are often used to increase performance. However, only few cores provide open interfaces for integrating such ISA Extensions (ISAX).
M. Damian, Julian Oppermann, Christoph Spang, A. Koch   +3 more
semanticscholar   +1 more source

Amyloid nomenclature 2024: update, novel proteins, and recommendations by the International Society of Amyloidosis (ISA) Nomenclature Committee

Amyloid: Journal of Protein Folding Disorders
The ISA Nomenclature Committee met at the XIX International Symposium of Amyloidosis in Rochester, MN, 27 May 2024. The in-person event was followed by many electronic discussions, resulting in the current updated recommendations.
J. N. Buxbaum, David S Eisenberg, M. Fändrich, Ellen D. McPhail, G. Merlini, Maria J. Saraiva, Yoshiki Sekijima, Per Westermark   +7 more
semanticscholar   +1 more source

Groundwater level simulation and forecasting using interior search algorithm-least square support vector regression (ISA-LSSVR)

, 2020
Least square support vector regression (LSSVR) is a powerful data-driven method for simulation and forecasting, with two parameters to tune. In this study, these parameters were automatically tuned using the interior search algorithm (ISA) and genetic ...
M. Moravej, P. Amani, Seyed‐Mohammad Hosseini‐Moghari   +2 more
semanticscholar   +1 more source

A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2020
Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements.
S. Bora, R. Paily
semanticscholar   +1 more source