Results 21 to 30 of about 6,792,843 (299)
Learning a Unified Latent Space for NAS: Toward Leveraging Structural and Symbolic Information
IEEE Access, 2022 Automatically designing neural architectures, i.e., NAS (Neural Architecture Search), is a promising path in machine learning. However, the main challenge for NAS algorithms is to reduce the considerable elapsed time to evaluate a proposed network.
Saeedeh Eslami +2 more
doaj +1 more source
REVIEW OF XY ROUTING ALGORITHM FOR NETWORK-ON-CHIP ARCHITECTURE [PDF]
, 2016 The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication is done through packet based networks. In NOC topology, routing algorithm and switching are main terminology .The routing algorithm is one of the key ...
CHAWADE, SHUBHANGI D +5 more
core +1 more source
IEEE Access, 2018 Caching at the edge of wireless networks is a promising means of alleviating the heavy burden of backhaul links and reducing the latency of transmission and handover in a cloud radio access network (C-RAN).
Jianmei Dai, Zhilong Zhang, Danpu Liu
doaj +1 more source
Scaling Analysis of Multilevel Polar Coded Modulation
IEEE Access, 2019 In this paper, we analyze and prove the capacity-achieving property of the equivalent asymmetric channels of multilevel polar-coded modulation in view of the scaling assuming regime, which employ some techniques of symmetric channels.
Kun Zhao +3 more
doaj +1 more source
The Alpha 21364 network architecture [PDF]
HOT 9 Interconnects. Symposium on High Performance Interconnects, 2002 The Alpha 21364 processor provides a high-performance, scalable, and reliable network architecture with a router that runs at 1.2 GHz and has a peak bandwidth of 22.4 Gbytes/s. Supporting configurations of up to 128 processors, this network architecture is well suited for communication-intensive server applications.
Shubhendu S. Mukherjee +4 more
openaire +2 more sources
Scalability of Network-on-Chip communication architecture for 3-D meshes. [PDF]
, 2009 Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems.
Pamunuwa, Dinesh Bandara +6 more
core +4 more sources
Implementation of QoS onto virtual bus network [PDF]
, 2009 Quality of Service (QoS) is a key issue in a multimedia environment because multimedia applications are sensitive to delay. The virtual bus architecture is a hierarchical access network structure that has been proposed to simplify network signaling.
Hassan, Rosilah +2 more
core +3 more sources
An Architecture for Active Networking [PDF]
, 1997 Active networking offers a change in the usual network paradigm: from passive carrier of bits to a more general computation engine. The implementation of such a change is likely to enable radical new applications that cannot be foreseen today.
Bhattacharjee, Samrat +2 more
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Architecture of a Network Monitoring Element [PDF]
15th IEEE International Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprises (WETICE'06), 2006 The scalability of a network monitoring system, a vital component of a Grid, is challenging. We propose a solution based on demand driven monitoring sessions that use passive network monitoring techniques on a domain oriented overlay network. Related aspects of security and group membership maintenance are also considered.
CIUFFOLETTI, AUGUSTO +1 more
openaire +4 more sources
Quarc: a novel network-on-chip architecture [PDF]
, 2008 This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC. The Quarc scheme significantly outperforms the Spidergon NoC through balancing the traffic which is the result of the modifications applied to the topology and ...
Moadeli, M. +8 more
core +1 more source