Results 21 to 30 of about 943 (76)
Research on Key Technologies of Unit‐Based CNC Machine Tool Assembly Design
Mathematical Problems in Engineering, Volume 2014, Issue 1, 2014., 2014 Assembly is the part that produces the maximum workload and consumed time during product design and manufacturing process. CNC machine tool is the key basic equipment in manufacturing industry and research on assembly design technologies of CNC machine tool has theoretical significance and practical value.
Zhongqi Sheng +4 more
wiley +1 more source
Wu’s Characteristic Set Method for SystemVerilog Assertions Verification
Journal of Applied Mathematics, Volume 2013, Issue 1, 2013., 2013 We propose a verification solution based on characteristic set of Wu’s method towards SystemVerilog assertion checking over digital circuit systems. We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied.
Xinyan Gao +4 more
wiley +1 more source
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs
VLSI Design, Volume 14, Issue 1, Page 53-64, 2002., 2002 A probabilistic equivalence checking method is developed based on the use of partial Haar Spectral Diagrams (HSDs). Partial HSDs are defined and used to represent a subset of Haar spectral coefficients for two Boolean functions. The resulting coefficients are then used to compute and to iteratively refine the probability that two functions are ...
M. A. Thornton +2 more
wiley +1 more source
Spectral Testing of Digital Circuits
VLSI Design, Volume 14, Issue 1, Page 83-105, 2002., 2002 Fault detection techniques using data compression methods have evolved during the last few years. Considerable work using individual Walsh spectral coefficients has been reported. In this paper, the application of spectral methods in testing of digital circuits with the emphasis on their usage for both input and output test compaction of digital ...
Bogdan J. Falkowski
wiley +1 more source
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model
VLSI Design, Volume 12, Issue 1, Page 69-79, 2001., 2001 Our aim is the development of a novel probabilistic method to estimate the power consumption of a combinational circuit under real gate delay model handling temporal, structural and input pattern dependencies. The chosen gate delay model allows handling both the functional and spurious transitions.
G. Theodoridis +3 more
wiley +1 more source
A Fast and Accurate Method of Power Estimation for Logic Level Networks
VLSI Design, Volume 12, Issue 2, Page 205-219, 2001., 2001 A method for estimating the power consumption of multilevel combinational networks is introduced. The proposed method has as inputs the signal probabilities, the data correlations of the primary inputs and the structure of the circuit, and consists of two major steps: (i) the calculation of the switching activity on an individual gate and (ii) the ...
G. Theodoridis +3 more
wiley +1 more source
Model‐integrated Tools for the Design of Dynamically Reconfigurable Systems
VLSI Design, Volume 10, Issue 3, Page 281-306, 2000., 2000 Several classes of modern applications demand very high performance from systems with minimal resources. These applications must also be flexible to operate in a rapidly changing environment. Achieving high performance from limited resources demands application‐specific architectures, while flexibility requires architectural adaptation capabilities ...
Ted Bapty +4 more
wiley +1 more source
Logic Synthesis for a Regular Layout
VLSI Design, Volume 10, Issue 1, Page 35-55, 1999., 1998 New algorithms for generating a regular two‐dimensional layout representation for multi‐output, incompletely specified Boolean functions, called, Pseudo‐Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post‐layout areas and delays before the layout is ...
Malgorzata Chrzanowska-Jeske +2 more
wiley +1 more source
IDDQ Detectable Bridges in Combinational CMOS Circuits
VLSI Design, Volume 5, Issue 3, Page 241-252, 1997., 1997 Undetectable stuck‐at faults in combinational circuits are related to the existence of logic redundancy (s-redundancy). Similarly, logically equivalent nodes may cause some bridging faults to become undetectable by IDDQ testing. An efficient method for the identification and removal of such functionally equivalent nodes (f-redundant nodes) in ...
E. Isern, J. Figueras
wiley +1 more source
Approximations by OBDDs and the Variable Ordering Problem [PDF]
, 2001 Ordered binary decision diagrams (OBDDs) and their variants are motivated by the need to represent Boolean functions in applications. Research concerning these applications leads also to problems and results interesting from theoretical point of view. In
Krause, Matthias +2 more
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