Results 11 to 20 of about 1,611,065 (368)

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

open access: yesInternational Journal of Reconfigurable Computing, 2012
A Hybrid router architecture for Networks-on-Chip “NoC” is presented, it combines Spatial Division Multiplexing “SDM” based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic ...
Angelo Kuti Lusala, Jean-Didier Legat
doaj   +2 more sources

Switching strategies in a class of packet switching networks [PDF]

open access: bronzeACM SIGARCH Computer Architecture News, 1983
This paper investigates some methods for improving the performance of Single Stage Shuffle Exchange Networks (SENs) and Multistage Interconnection Networks (MINs). The three new switching strategies proposed use extra buffers to enhance performance. Approximate analysis and simulation results indicate significant improvement in performance for both ...
Manoj Kumar, D.M. Dias, J. Robert Jump
  +6 more sources

Design of all Optical Packet Switching Networks

open access: diamondSultan Qaboos University Journal for Science, 2002
Optical switches and wavelength converters are recognized as two of the most important DWDM system components in future all-optical networks. Optical switches perform the key functions of flexible routing, reconfigurable optical cross-connect (OXC ...
Hussein T. Mouftah
doaj   +3 more sources

Optical packet switching without packet alignment [PDF]

open access: green24th European Conference on Optical Communication. ECOC '98 (IEEE Cat. No.98TH8398), 2002
Operation without packet alignment of an all-optical packet switch is proposed and predicted feasible through a detailed traffic analysis. Packet alignment units are eliminated resulting in a simple switch architecture while optimal traffic performance is maintained through the flexibility provided by WDM.
P.B. Hansen   +2 more
openalex   +3 more sources

Virtual clock: a new traffic control algorithm for packet switching networks [PDF]

open access: greenConference on Applications, Technologies, Architectures, and Protocols for Computer Communication, 1990
Lizhong Zhang
openalex   +2 more sources

Deadlock in Packet Switching Networks [PDF]

open access: yes, 2021
A deadlock in a packet switching network is a state in which one or more messages have not yet reached their target, yet cannot progress any further. We formalize three different notions of deadlock in the context of packet switching networks, to which we refer as global, local and weak deadlock. We establish the precise relations between these notions,
Anna Stramaglia   +2 more
openaire   +4 more sources

Nanosecond optical switching and control system for data center networks

open access: yesNature Communications, 2022
Electrical switching based data center networks have an intrinsic bandwidth bottleneck and, require inefficient and power-consuming multi-tier switching layers to cope with the rapid growing traffic in data centers.
X. Xue, N. Calabretta
semanticscholar   +1 more source

Quantum key distribution in a packet-switched network

open access: yesnpj Quantum Information, 2023
Packet switching revolutionized the Internet by allowing the efficient use of network resources for data transmission. In a previous work, we introduced packet switching in quantum networks as a path to the Quantum Internet and presented a proof-of ...
Reem Mandil   +3 more
doaj   +1 more source

On-Board Switching for Space-Integrated-Ground Information Network: Progress and Trends

open access: yes天地一体化信息网络, 2021
Considering the requirements of the space-integrated-ground information network, the technologies of on-board channelized switching and the technologies of on-board packet switching were surveyed.Among, the discussed channelized switching technologies ...
Hao WU   +5 more
doaj   +2 more sources

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

open access: yesMicromachines, 2023
Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications.
Xinbing Zhou, Peng Hao, Dake Liu
doaj   +1 more source

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