Results 21 to 30 of about 1,504,271 (353)
Quality Assessment of Dual-Parallel Edge Deblocking Filter Architecture for HEVC/H.265
Applied Sciences, 2022 Preserving the visual quality is a major constraint for any algorithm in image and video processing applications. AVC and HEVC are the extensively used video coding standards for various video processing applications in recent days.
Prayline Rajabai Christopher +1 more
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Heliyon, 2023 Previous research has presented conflicting evidence regarding whether Chinese characters are processed holistically. In past work, we applied Systems Factorial Technology (SFT) and discovered that native Chinese speakers exhibited limited capacity when ...
Hanshu Zhang +4 more
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Air pollution modelling using a graphics processing unit with CUDA [PDF]
, 2009 The Graphics Processing Unit (GPU) is a powerful tool for parallel computing. In the past years the performance and capabilities of GPUs have increased, and the Compute Unified Device Architecture (CUDA) - a parallel computing architecture - has been ...
Lagzi, Istvan +3 more
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Emerging Science Journal, 2017 Processors are main part of the calculation and decision making of a system. Today, due to the increasing need of industry and technology to faster and more accurate computing power, design and manufacture of parallel processing units, has been very much
Ali Hadizadeh, Ehsan Tanghatari
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Distributed Parallel Architecture for "Big Data" [PDF]
Informatică economică, 2012 This paper is an extension to the "Distributed Parallel Architecture for Storing and Processing Large Datasets" paper presented at the WSEAS SEPADS’12 conference in Cambridge.
Catalin BOJA +2 more
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Efficient Architecture-Aware Acceleration of BWA-MEM for Multicore Systems [PDF]
IEEE International Parallel and Distributed Processing Symposium, 2019 Innovations in Next-Generation Sequencing are enabling generation of DNA sequence data at ever faster rates and at very low cost. For example, the Illumina NovaSeq 6000 sequencer can generate 6 Terabases of data in less than two days, sequencing nearly ...
Md. Vasimuddin +3 more
semanticscholar +1 more source
New efficient network architecture BSN-MOT for parallel processing
Tongxin xuebao, 2014 BSN-MOT as a two-tier architecture that takes the advantages of both the BSN and the MOT was presented. Topological property and many communication and application algorithms are investigated.
Jiang-yun LI, Li-ting SUN
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FPGA-Based Hardware Design for Scale-Invariant Feature Transform
IEEE Access, 2018 This paper proposes a novel hardware design method of scale-invariant feature transform (SIFT) algorithm for implementation on field-programmable gate array (FPGA).
Shih-An Li +4 more
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An Efficient and Scalable Semiconductor Architecture for Parallel Automata Processing
IEEE Transactions on Parallel and Distributed Systems, 2014 We present the design and development of the automata processor, a massively parallel non-von Neumann semiconductor architecture that is purpose-built for automata processing.
Paul Dlugosch +4 more
semanticscholar +1 more source
An Efficient Parallel Gauss-Seidel Algorithm on a 3D Torus Network-on-Chip
Sultan Qaboos University Journal for Science, 2015 Network-on-chip (NoC) multi-core architectures with a large number of processing elements are becoming a reality with the recent developments in technology.
Khaled Day, Mohammad H. Al-Towaiq
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