Results 301 to 310 of about 1,504,271 (353)

Parallel processing architectures for image processing systems

SPIE Proceedings, 1995
Recent image processing systems are exploiting available high computing throughputs in parallel processing architectures. Algorithms are becoming more adaptive to specific clutter and scene content. Data dependencies are being used for more robust operation. This, in turn, increases the number of compute operations required per pixel or image frame.
Michael Vahey, Robert F. Cody
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A parallel architecture for video processing

1997
Video data consists of a sequence of frames that is produced at a constant rate and many applications in real-time require the processing of these frames executing compute intensive algorithms. To handle many of such applications in real-time, we developed a new architecture based on parallel processing.
Yakup Paker, D. Turgay Altilar, A. Vahit Sahiner   +2 more
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Experimental Application-Driven Architecture Analysis of an SIMD/MIMD Parallel Processing System

IEEE Trans. Parallel Distributed Syst., 1990
An experimental analysis of the architecture of an SIMD/MIMD parallel processing system is presented. Detailed implementations of parallel fast Fourier transform (FFT) programs were used to examine the performance of the prototype of the PASM ...
E. Bronson, T. Casavant, L. Jamieson
semanticscholar   +1 more source

Parallel architectures for image processing

COMPSAC 79. Proceedings. Computer Software and The IEEE Computer Society's Third International Applications Conference, 1979., 1981
Conventional computers do not readily lend themselves to picture processing. Digital image manipulation by conventional computer is accomplished only at a tremendous cost in time and conceptual distraction. Computer image processing is the activity of modifying a picture such that retrieval of relevant pictorially encoded information becomes trivial ...
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Architectures For Parallel Image Processing

SPIE Proceedings, 1985
Images taken by airborne and laboratory sensors have been used for many purposes including autonomous guidance, robot vision, medical diagnosis, automated inspection and automated measurements. Scene recognition operations are relatively costly in computing time due to the large amount of data needed to be analyzed.
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Parallel Image Processing with the Block Data Parallel Architecture

IBM Journal of Research and Development, 1996
Many digital signal and image processing algorithms can be speeded up by executing them in parallel on multiple processors. The speed of parallel execution is limited by the need for communication and synchronization between processors. In this paper, we present a paradigm for parallel processing that we call the block data flow paradigm (BDFP).
Douglas S. Reeves, Winser E. Alexander, Clay Gloster   +2 more
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A Parallel Architecture for Stereoscopic Processing

1999
An embedded pipeline/parallel architecture to support an extended quad-tree algorithm suitable for real-time estimation of the dense disparity map (DDM) for stereoscopic image processing is proposed. The system performance has been analyzed by several simulations to qualify the results by both an objective measurement (Mean Square Error) and a ...
Bruno Ciciani, Milton Romero
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Parallel processing computer architectures for process control

Proceedings of the Thirty-Fourth Southeastern Symposium on System Theory (Cat. No.02EX540), 2003
Modern, large-scale, high-speed process control automation is quite complex in nature. Continuous manufacturing processes currently in use require advanced computer technologies such as simultaneous parallel processing architecture for synchronous process operations that take place independent of each other.
H. Abachi, G. Venkatesan
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Parallel processing architectures for STAP

2004
This chapter describes the methodologies for online processing of the received radar data by a set of N antennas and M pulse repetition intervals (PRIs) for the calculation of space-time adaptive (STAP) filter output. The numerically robust and computationally efficient QR-decomposition (QRD) is used to derive the so-called MVDR (minimum variance ...
Alfonso Farina, Luca Timmoneri
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An architecture and a simulator for parallel signal processing

Proceedings of Southeastcon '93, 2002
The real-time implementation of many digital signal processing (DSP) algorithms requires novel algorithm mapping methods and architectures. Some of the architectures developed thus far include data-flow systems, systolic arrays, and wavefront arrays. Ideas from these architectures are combined with the concept of block data flow processing to present ...
S.T. Alexandre, Winser E. Alexander, D.S. Reeves   +2 more
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