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Parallel video processing on FPGA architecture
International Journal of High Performance Systems Architecture, 2018Real-time video applications are becoming widely used in many domains with more demand for high performance. Video processing is intensive and habitually has accompanying real-time or super-real-time requirements. Such us, multiple cameras are used in monitoring and surveillance systems in automatically real-time analyse video to detect unusual events.
Lamjed Touil +5 more
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A parallel processing architecture for image understanding
Systems and Computers in Japan, 1991AbstractGeneral‐purpose image understanding requires that an image understanding system be built that will accommodate multiple image understanding algorithms and thereby provide the system with flexibility and robustness. This paper proposes a mechanism whereby multiple modules can cooperate with each other and process in parallel, each of which ...
Yuichi Ohta +2 more
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A Parallel Architecture perspective on language processing
Brain Research, 2007This article sketches the Parallel Architecture, an approach to the structure of grammar that contrasts with mainstream generative grammar (MGG) in that (a) it treats phonology, syntax, and semantics as independent generative components whose structures are linked by interface rules; (b) it uses a parallel constraint-based formalism that is ...
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Parallel vision processing and dedicated parallel architectures
Proceedings International Parallel and Distributed Processing Symposium, 2004This paper proposes an overview of different processing paradigms inherent to image and vision processing, and of hardware support for them. It identifies some still open questions in parallel image/vision processing. The paper is organized into four parts.
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Optimizing Architectures For Parallel FFT Processing
SPIE Proceedings, 1989In the design of high-performance embedded processor systems dedicated to a predefined range of tasks, the best designs will result from the simultaneous optimization of the hardware architecture and the algorithms for the required task suite. This paper presents studies in progress of techniques for such optimizations applied to synthetic-aperture ...
J. D. Sisk, R. K. Bardin
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Chip architectures for parallel processing
Electronics and Power, 1985Chip architectures designed to implement parallel algorithms can achieve very high processing rates and, as such, are becoming important in signal processing. Such chips are particularly amenable to VLSI design and this is likely to encourage their development and extend their areas of ...
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Asynchronous Design for Parallel Processing Architectures.
1991Abstract : As the integration of VLSI systems becomes larger and denser, implementing a high-performance parallel architecture using a global clock is becoming more inefficient and difficult to design, primarily due to concerns related to clock skew and data synchronization.
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Models of reading aloud: Dual-route and parallel-distributed-processing approaches.
, 1993It has often been argued that various facts about skilled reading aloud cannot be explained by any model unless that model possesses a dual-route architecture (lexical and nonlexical routes from print to speech).
M. Coltheart +3 more
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On Parallel Reconfigurable Architectures for Image Processing
1999This paper proposes a short overview analysing the adequation between image processing requirements, parallel reconfigurable architectures dedicated to image processing and parallel computing. Through some examples of academic prototypes and commercialised computers the evolution of concepts useful for efficient and real time image processing is shown.
Edwige E. Pissaloux, Edwige E. Pissaloux
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Parallel processing architectures for reconfigurable systems
2003 Design, Automation and Test in Europe Conference and Exhibition, 2003Novel reconfigurable computing architectures exploit the inherent parallelism available in many signal-processing problems. These architectures often consist of networks of compute elements that have an ALU-like structure with corresponding instructions. This opens opportunities for rapid dynamic reconfiguration and instruction multiplexing.
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