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Hmesh: A vlsi architecture for parallel processing

1986
Enhancements to array processors in the form of broadcast buses have been proposed for improving the speeds of algorithms in linear algebra, image processing and computational geometry. In this paper, we consider certain practical issues in such arrays which include fewer processors connected to the broadcast buses and finite time, namely log N time ...
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Parallel Processing Architecture of Remotely Sensed Image Processing System Based on Cluster

International Congress on Image and Signal Processing, 2009
Hangye Liu   +3 more
semanticscholar   +1 more source

Parallel processing architecture for micro-polygon rasterization

2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES, 2013
The shape of an object displayed on-screen is specified by a collection of triangles, or micro-polygons. Micro-polygons are defined by the (x,y,z) co-ordinates of the three vertices. Rasterization uses the vertex locations of the micropolygon to determine the co-ordinates of all the pixels covered by the micro-polygon on the display screen.
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A Fault Tolerant Massively Parallel Processing Architecture

J. Parallel Distributed Comput., 1987
V. Balasubramanian, P. Banerjee
semanticscholar   +1 more source

A pixel level parallel processing architecture for multi-standard video codec

2006 Digest of Technical Papers International Conference on Consumer Electronics, 2006
T. Tanaka   +4 more
semanticscholar   +1 more source

A transputer architecture for parallel processing of polygonal regions

1990
The growing interest in computer graphics has to be faced with the great complexity of many practical applications, as for example digital mapping. This paper discusses a solution in the field of parallel management of polygonal regions. The proposal is designed according with an integrated approach towards the definition of a data representation ...
andrea tomasi, claudio montani
openaire   +3 more sources

An FPGA implementation of a flexible, parallel image processing architecture suitable for embedded vision systems

Proceedings International Parallel and Distributed Processing Symposium, 2003
S. McBader, P. Lee
semanticscholar   +1 more source

A scalable processing-in-memory accelerator for parallel graph processing

International Symposium on Computer Architecture, 2015
Junwhan Ahn   +4 more
semanticscholar   +1 more source

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