Results 71 to 80 of about 31,720 (268)

Fundamental Challenges, Physical Implementations, and Integration Strategies for Ising Machines in Large‐Scale Optimization Tasks

Advanced Electronic Materials, EarlyView.
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley   +1 more source

Electrode‐Engineered Dual‐Mode Multifunctional Lead‐Free Perovskite Optoelectronic Memristors for Neuromorphic Computing

Advanced Electronic Materials, EarlyView.
A lead‐free perovskite memristive solar cell structure that call emulate both synaptic and neuronal functions controlled by light and electric fields depending on top electrode type. ABSTRACT Memristive devices based on halide perovskites hold strong promise to provide energy‐efficient systems for the Internet of Things (IoT); however, lead (Pb ...
Michalis Loizos, Konstantinos Rogdakis, Konstantinos Chatzimanolis, Katerina Anagnostou, Emmanuel Kymakis   +4 more
wiley   +1 more source

On the Role of Preprocessing and Memristor Dynamics in Reservoir Computing for Image Classification

Advanced Electronic Materials, EarlyView.
ABSTRACT Reservoir computing (RC) is an emerging recurrent neural network architecture that has attracted growing attention for its low training cost and modest hardware requirements. Memristor‐based circuits are particularly promising for RC, as their intrinsic dynamics can reduce network size and parameter overhead in tasks such as time‐series ...
Rishona Daniels, Duna Wattad, Ronny Ronen, David Saad, Shahar Kvatinsky   +4 more
wiley   +1 more source

Figures of Argument (OSSA 2005 Keynote Address)

Informal Logic, 2004
From the seventeenth through the nineteenth centuries, scientists such as Kekule, Mendel, Lavoisier and Harvey argued for insights that depended critically on antithetical expressions and reasoning.
Jeanne Fahnestock
doaj   +1 more source

Automatically Tuning Parallel and Parallelized Programs [PDF]

, 2010
In today's multicore era, parallelization of serial code is essential in order to exploit the architectures' performance potential. Parallelization, especially of legacy code, however, proves to be a challenge as manual efforts must either be directed towards algorithmic modifications or towards analysis of computationally intensive sections of code ...
Dave, Chirag, Eigenmann, Rudolf
openaire   +2 more sources

Experimental Demonstration of Temporally Aware Fault‐Tolerant Sensor Fusion Using Memristive Associative Learning

Advanced Electronic Materials, EarlyView.
In dynamic driving scenarios, the proposed approach ensures only temporally aligned sensor inputs to make driving decisions, preventing false activations. By enabling selective hardware‐level learning, it achieves fast, reliable responses under noisy conditions.
Kapil Bhardwaj, Ashfak Nehal, Dmitrii Semenov, Roman Sotner, Sayani Majumdar   +4 more
wiley   +1 more source

Managing Parallelism in Parallel Systems.

Comput. Artif. Intell., 1995
A fundamental problem of parallel computing is that applications often require  large-size instances of an algorithm while parallel systems are generally hardwired architectures which cannot be easily reconfigured according to program size or structure.
openaire   +1 more source

Highly‐Uniform Passive Crossbar Arrays of Resistive Switching Random Access Memory (RRAM) for In‐Memory Computing Applications

Advanced Electronic Materials, EarlyView.
Passive resistive memory arrays promise efficient in‐memory computing but suffer from sneak paths and programming variability. Here, highly uniform 32 × 32 passive RRAM crossbars are programmed with multilevel precision below 3% error and 99.5% yield.
S. Ricci, P. Mannocci, M. Porzani, D. Bridarolli, F. Carletti, M. Farronato, D. Ielmini   +6 more
wiley   +1 more source

Performance Analysis of High Throughput MAP Decoder for Turbo Codes and Self Concatenated Convolutional Codes

IEEE Access, 2019
The effect of parallelism on Bit Error Rate (BER) performance of Turbo Code (TC) and Self Concatenated Convolutional Code (SECCC) with different levels of parallelism and frame sizes is investigated. Next Iteration Initialization (NII) method is employed
Farzana Shaheen, Muhammad Fasih Uddin Butt, Shahrukh Agha, Soon Xin Ng, Robert G. Maunder   +4 more
doaj   +1 more source

Balancing Pipeline Parallelism with Vocabulary Parallelism

CoRR
Pipeline parallelism is widely used to scale the training of transformer-based large language models, various works have been done to improve its throughput and memory footprint. In this paper, we address a frequently overlooked issue: the vocabulary layers can cause imbalanced computation and memory usage across pipeline stages, worsening pipeline ...
Man Tsung Yeung, Penghui Qi, Min Lin, Xinyi Wan   +3 more
openaire   +3 more sources