Design of Low-Latency Layered Normalized Minimum Sum Low-Density Parity-Check Decoding Based on Entropy Feature for NAND Flash-Memory Channel. [PDF]
Li Y, Hu H.
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MALDI-TOF MS for malaria vector surveillance: A cost-comparison analysis using a decision-tree approach. [PDF]
Karisa J +12 more
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Two-Phase Globally Coupled Low-Density Parity Check Decoding Aided with Early Termination and Forced Convergence. [PDF]
Zhu K, Yang H.
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High-rate quantum LDPC codes for long-range-connected neutral atom registers. [PDF]
Pecorari L +3 more
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New quantum LDPC codes based on projective geometry. [PDF]
Tang C, Bai C, Feng Y.
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A Family of Optimal Linear Functional-Repair Regenerating Storage Codes. [PDF]
Hollmann HDL.
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BCK-codes Based on a Parity Check Matrix
Fundamenta Informaticae, 2020Hamming codes are of primary concern in information theory and its applications. Despite a number of researches that have been conducted on such codes and their characterizations, dealing with the properties of previously introduced codes in a BCK-algebraic framework has not been considered in earlier works.
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FPGA implementation of Parity Check Matrix based Low Density Parity Check Decoder
2018 2nd International Conference on Inventive Systems and Control (ICISC), 2018Low Density Parity Check (LDPC) error correction decoders have become popular in diverse communication systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. Low Density Parity Check Decoder is a class of Forward Error Correction Codes.
H. Praveena, K. Kalyani
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Efficient architectures for parity check matrix generation
2015 23rd Telecommunications Forum Telfor (TELFOR), 2015New advanced decoding algorithms for error correction systems can improve the frame error rate over commonly used systems. However, they also pose new challenges for their hardware implementations. One part, which consumes a considerable amount of hardware resources, is the storage of the parity check matrix.
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