Results 191 to 200 of about 108,131 (252)

MALDI-TOF MS for malaria vector surveillance: A cost-comparison analysis using a decision-tree approach. [PDF]

PLoS One
Karisa J, Rist C, Tuwei M, Ominde K, Bartilol B, Ondieki Z, Musani H, Wanjiku C, Mwangangi J, Mbogo C, Rono M, Bejon P, Maia M.   +12 more
europepmc   +1 more source

Two-Phase Globally Coupled Low-Density Parity Check Decoding Aided with Early Termination and Forced Convergence. [PDF]

Sensors (Basel)
Zhu K, Yang H.
europepmc   +1 more source

High-rate quantum LDPC codes for long-range-connected neutral atom registers. [PDF]

Nat Commun
Pecorari L, Jandura S, Brennen GK, Pupillo G.   +3 more
europepmc   +1 more source

New quantum LDPC codes based on projective geometry. [PDF]

Sci Rep
Tang C, Bai C, Feng Y.
europepmc   +1 more source

A Family of Optimal Linear Functional-Repair Regenerating Storage Codes. [PDF]

Entropy (Basel)
Hollmann HDL.
europepmc   +1 more source

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BCK-codes Based on a Parity Check Matrix

Fundamenta Informaticae, 2020
Hamming codes are of primary concern in information theory and its applications. Despite a number of researches that have been conducted on such codes and their characterizations, dealing with the properties of previously introduced codes in a BCK-algebraic framework has not been considered in earlier works.
Keshavarzian, Nazanin, Borumand Saeid, Arsham, Tehranian, Abolfazl   +2 more
openaire   +2 more sources

FPGA implementation of Parity Check Matrix based Low Density Parity Check Decoder

2018 2nd International Conference on Inventive Systems and Control (ICISC), 2018
Low Density Parity Check (LDPC) error correction decoders have become popular in diverse communication systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. Low Density Parity Check Decoder is a class of Forward Error Correction Codes.
H. Praveena, K. Kalyani
openaire   +1 more source

Efficient architectures for parity check matrix generation

2015 23rd Telecommunications Forum Telfor (TELFOR), 2015
New advanced decoding algorithms for error correction systems can improve the frame error rate over commonly used systems. However, they also pose new challenges for their hardware implementations. One part, which consumes a considerable amount of hardware resources, is the storage of the parity check matrix.
Stefan Scholl, Norbert When
openaire   +1 more source

Tiling parity-check matrix for reduced complexity high throughput low-density parity-check decoders

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005., 2006
An approach for reducing hardware complexity of LDPC decoders is presented in this paper. Low-density parity-check (LDPC) codes have a sparse parity-check matrix (H matrix). In LDPC decoder, the H matrix is stored in memory and contains information about the parity check constraints. The approach presented in this paper constructs several sub-matrices (
A. Selvarathinam, null Gwan Choi
openaire   +1 more source

Design of Rate-Compatible Low-Density Parity-Check Codes with Constant Check Matrix

2020 International Conference Engineering and Telecommunication (En&T), 2020
In this paper, we propose a “bit duplication” design method for rate-compatible low-density parity-check codes (LDPC). The main idea of the method is to change the structure of codewords during its transmission over the communication system. This method can be effectively applied to create a set of codes, allowing to obtain lower-rate codes from the ...
Son Le, Evgeny Likhobabin
openaire   +1 more source