Results 201 to 210 of about 17,714 (263)
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ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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2018 IEEE Custom Integrated Circuits Conference (CICC), 2018
▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
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▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
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IEEE Transactions on Communications, 1977
A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null.
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A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null.
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A frequency steered phase locked loop
1997 IEEE International Performance, Computing and Communications Conference, 1997Voltage controlled oscillators (VCOs) implemented in digital VLSI IC (integrated circuit) technology typically have very poorly controlled centre frequencies and poor phase noise characteristics, thus severely limiting their use in phase locked loop (PLL) applications.
Martin T. Hill, Antonio Cantoni
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A digital loop filter for a Phase Locked Loop
2011 17th International Conference on Digital Signal Processing (DSP), 2011Modern digital telecommunication and audio systems include a Digital Phase Locked Loop (D-PLL) in a form of a device or an algorithm. Wireless infrastructure, broadband wire-line networks and high end audio systems require very high performance PLLs.
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On the Pull-In Range of Phase-Locked Loops
IEEE Transactions on Communications, 1975The problem of determining the pull-in range of phaselocked loops is solved indirectly by evaluating the limit cycles of the loop in which the frequency error has a constant average. The analytical results derived here are in complete agreement with simulation results.
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On Stochastic Phase-Lock Loop Solutions
IEEE Transactions on Communications, 1976The solutions to stochastic first- and second-order phaselock loop differential equations are studied in the sense of the calculus of Ito and Stratonovich. The solutions are found to be both theoretically and experimentally invariant to the calculus used.
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2002
In this chapter we describe an important electronic circuit, the phase-locked loop (PLL). We first investigate the circuit’s dynamics without and with random perturbations, but in the absence of external forcing. Then we analyze the response of the circuit to noisy external signals, and we describe a method for extracting signals from the result.
Anatoli V. Skorokhod +2 more
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In this chapter we describe an important electronic circuit, the phase-locked loop (PLL). We first investigate the circuit’s dynamics without and with random perturbations, but in the absence of external forcing. Then we analyze the response of the circuit to noisy external signals, and we describe a method for extracting signals from the result.
Anatoli V. Skorokhod +2 more
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2012
Arguably the most important circuit in modern electronics is a PLL. A PLL is embedded into virtually every piece of modern electronic equipment: computers, wireless communication systems, and test equipment, to name a few. What is more, each of the subsystem blocks inside these systems may contain their own PLL sub-circuit manufactured in an IC ...
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Arguably the most important circuit in modern electronics is a PLL. A PLL is embedded into virtually every piece of modern electronic equipment: computers, wireless communication systems, and test equipment, to name a few. What is more, each of the subsystem blocks inside these systems may contain their own PLL sub-circuit manufactured in an IC ...
openaire +1 more source